LTC3883 Datasheet, PDF (8/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Electrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T_A = 25°C (Note 2). V_IN = 12V, V_RUN = 3.3V, f_SYNC = 500kHz (externally
driven) unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
Digital Inputs SHARE_CLK, WP
V_IH
Input High Threshold Voltage
V_IL
Input Low Threshold Voltage
Leakage Current SDA, SCL, ALERT, RUN
l
l 0.6
I_OL
Input Leakage Current
0V ≤ V_PIN ≤ 5.5V
l
Leakage Current GPIO, PGOOD
I_GL
Input Leakage Current
0V ≤ V_PIN ≤ 3.6V
l
Digital Filtering of GPIO
I_FLTG
Input Digital Filtering GPIO
Digital Filtering of RUN
I_FLTG
Input Digital Filtering RUN
PMBus Interface Timing Characteristics
f_SCL
t_BUF
t_HD,STA
Serial Bus Operating Frequency
Bus Free Time Between Stop and Start
Hold time After Repeated Start Condition.
After this Period, the First Clock is Generated
l 10
l 1.3
l 0.6
t_SU,STA
t_SU,STO
t_HD,DAT
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
Receiving Data
Transmitting Data
l 0.6
l 0.6
l
0
l 0.3
t_SU,DAT
Data Setup Time
Receiving Data
l 0.1
t_{TIMEOUT_SMB} Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
Measured from the Last PMBus Start Event
t_LOW
Serial Clock Low Period
t_HIGH
Serial Clock High Period
l 1.3
l 0.6
TYP MAX
1.5
1.8
1.0
±5
±2
3
10
400
0.9
32
150
10000
UNITS
V
V
µA
µA
µs
µs
kHz
µs
µs
µs
µs
µs
µs
µs
ms
ms
µs
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3883/LTC3883-1 are tested under pulsed load conditions
such that T_J ≈ T_A. The LTC3883E/LTC3883E-1 are guaranteed to meet
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 105°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3883I/LTC3883I-1 are guaranteed over the full –40°C to 125°C operating
junction temperature range. T_J is calculated from the ambient temperature,
T_A, and power dissipation, P_D, according to the following formula:
T_J = T_A + (P_D • θ_JA)
The maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 6: The data conversion is done in round robin fashion. All inputs
signals are continuously converted for a typical latency of 120ms.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as
read from READ_IOUT in amperes.
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 •
[Zero Code Offset + ADC Linearity Error]/Actual Value.
Note 9: All V_OUT commands assume the ADC is used to auto-zero the
output to achieve the stated accuracy. LTC3883 is tested in a feedback
loop that servos V_OUT to a specified value.
Note 10: The maximum V_OUT voltage is 5.5V.
Note 11: The maximum V_IN voltage is 28V.
Note 12: When V_IN < 6V, INTV_CC must be tied to V_IN.
Note 13: EEPROM endurance is guaranteed by design, characterization
and correlation with statistical process controls. Data retention is
production tested via a high temperature bake at wafer level.The minimum
retention specification applies for devices whose EEPROM has been cycled
3883f
8