LTC3883 Datasheet, PDF (13/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Pin Functions
FREQ_CFG (Pin 14): Frequency or Phase Set/Select Pin.
Connect a ±1% resistor divider between the chip V_DD25
FREQ_CFG and GND in order to select switching frequency
or phase. If the pin is left open, the IC will use the value
programmed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
V_{OUT_CFG} (Pin 15): Output Voltage Select Pin. Connect a
±1% resistor divider between the chip V_DD25, V_{OUT_CFG}
and SGND in order to select output voltage. This voltage
can be adjusted with the V_{TRIM_CFG} pins. If the pin is left
open, the IC will use the value programmed in the NVM.
Minimize capacitance when the pin is open to assure ac-
curate detection of the pin state.
V_{TRIM_CFG} (Pin 17): Voltage Trim Select Pin. Connect a
±1% resistor divider between the chip V_DD25, V_{TRIM_CFG}
and SGND in order to adjust the output voltage set point.
The V_{TRIM_CFG} settings in conjunction with the V_{OUT_CFG}
setting adjusts the voltage set point. If the pin is left open,
the IC will either not modify the V_{OUT_CFG} setting or use
NVM. Minimize capacitance when the pin is open to assure
accurate detection of the pin state.
V_DD25 (Pin 18): Internally Generated 2.5V Power Supply
Output. Bypass this pin to GND with a low ESR 1μF capaci-
tor. Do not load this pin with external current.
WP (Pin 19): Write Protect Pin Active High. An internal
10µA current source pulls the pin to V_DD33. If WP is high,
the PMBus writes are restricted.
SHARE_CLK (Pin 20): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used to
synchronize the timing between multiple LTC3883s.
Tie all the SHARE_CLK pins together. All LTC3883s will
synchronize to the fastest clock. An equivalent pull-up
resistance of 5.49k to V_DD33 is required.
V_DD33 (Pin 21): Internally Generated 3.3V Power Supply
Output. Bypass this pin to GND with a low ESR 1μF capaci-
tor. Do not load this pin with external current.
SW (Pin 22): Switch Node Connection to the Inductor.
Voltage swings at the pins are from a Schottky diode
(external) voltage drop below ground to V_IN.
TG (Pin 23): Top Gate Driver Output. This is the output of
the floating driver with a voltage swing equal to INTV_CC
superimposed on the switch node voltage.
BOOST (Pin 24): Boosted Floating Driver Supply. The (+)
terminal of the booststrap capacitor connects to this pin.
This pin swings from a diode voltage drop below INTV_CC
up to V_IN + INTV_CC.
PGND (Pin 25): Power Ground Pin. Connect this pin closely
to the source of the bottom N-channel MOSFET, the (–)
terminal of C_INTVCC and the (–) terminal of C_IN.
BG (Pin 26): Bottom Gate Driver Output. This pin drives
the gates of the bottom N-channel MOSFET between
PGND and INTV_CC.
INTV_CC (Pin 27, LTC3883): Internal Regulator 5V Out-
put. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7μF low
ESR tantalum or ceramic capacitor.
EXTV_CC (Pin 27, LTC3883-1): External Regulator 5V
input. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor.
V_IN (Pin 28): Main Input Supply. Decouple this pin to PGND
with a capacitor (0.1µF to 1µF). For applications where
the main input power is 5V, tie the V_IN and INTV_CC pins
together. If the input current sense amplifier is not used,
this pin must be shorted to the V_{IN_SNS} and I_{IN_SNS} pins.
I_TH (Pin 29): Current Control Threshold and Error Ampli-
fier Compensation Node. The current comparator tripping
threshold increases with the I_TH voltage.
V_SENSE+ (Pin 30): Positive Voltage Sense Input.
V_SENSE– (Pin 31): Negative Voltage Sense Input.
TSNS (Pin 32): External Diode Temperature Sense. Connect
to the anode of a diode-connected PNP transistor and star
connect the cathode to GND in order to sense remote
temperature. If an external temperature sense element is not
installed, short pin to ground and set the UT_FAULT_LIMIT
to –275°C, set the UT_FAULT_RESPONSE to ignore, and
set IOUT_CAL_GAIN_TC to 0.
GND (Exposed Pad Pin 33): Ground. All small-signal and
compensation components should connect to this ground,
which in turn connects to PGND at one point.
3883f
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