LTC3883 Datasheet, PDF (46/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Applications Information
do not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3883, ceramic capacitors
can also be used for C_IN. Always consult the manufacturer
if there is any question.
The benefit of using two LTC3883 2-phase operation can
be calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common C_IN(s). Separating the sources and C_IN may pro-
duce undesirable voltage and current resonances at V_IN.
A small (0.1µF to 1µF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3883, is also
suggested. A 2.2Ω – 10Ω resistor placed between C_IN
(C1) and the V_IN pin provides further isolation between
the two LTC3883s.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V_OUT) is approximated by:
∆V_OUT
≈ I_RIPPLE
 _ESR
+
1
8fC_OUT


where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the
inductor. The output ripple is highest at maximum input
voltage since I_RIPPLE increases with input voltage.
Fault Conditions
The LTC3883 GPIO pin is configurable to indicate a variety
of faults including OV, UV, OC, OT, timing faults, peak
overcurrent faults. In addition the GPIO pin can be pulled
low by external sources indicating a fault in some other
portion of the system. The fault response is configurable
and allows the following options:
n _Ignore
n _{Shut Down Immediately—Latch Off}
n _{Shut Down Immediately—Retry Indefinitely at the Time}
Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
The OV response is automatic. If an OV condition is de-
tected, TG goes low and BG is asserted.
Fault logging is available on the LTC3883. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTC3883 internal temperature is in excess of 85°C,
the write into the NVM is not recommended. The data will
still be held in RAM, unless the 3.3V supply UVLO thresh-
old is reached. If the die temperature exceeds 130°C all
NVM communication is disabled until the die temperature
drops below 120°C.
3883f
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