LTC3883 Datasheet, PDF (47/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Applications Information
Open-Drain Pins
The LTC3883 has the following open-drain pins:
3.3V Pins
1. GPIO
2. SYNC
3. SHARE_CLK
4. PGOOD
5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUN
2. ALERT
3. SCL
4. SDA
All the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low threshold on the pins
is 1.4V; thus, plenty of margin on the digital signals with
3mA of current. For 3.3V pins, 3mA of current is a 1.1k
resistor. Unless there are transient speed issues associ-
ated with the RC time constant of the resistor pull-up and
parasitic capacitance to ground, a 10k resistor or larger
is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
R_PULLUP
=
3
t_RISE
• 100pF
=
1k
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capaci-
tance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is one time constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
oscillator is set for 500kHz and the load is 100pF and a
3x time constant is required, the resistor calculation is
as follows:
R_PULLUP
=
2µs – 500ns
3 • 100pF
=
5k
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and determine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
Phase-Locked Loop and Frequency
Synchronization
The LTC3883 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by the
lower 3 bits of the MFR_PWM_CONFIG_LTC3883 com-
mand. For PolyPhase applications, it is recommended all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
250kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
The PLL has a lock detection circuit. If the PLL should lose
lock during operation, bit 4 of the STATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low.
The fault can be cleared by writing a 1 to the bit. If the
user does not wish to see the PLL_FAULT, even if a
synchronization clock is not available at power up, bit 3
of the MFR_CONFIG_ALL_LTC3883 command must be
asserted.
3883f
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