LTC3883 Datasheet, PDF (49/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Applications Information
Both the V_{IN_SNS} and I_{IN_SNS} pins need to be filtered
with a 1% tolerance 100Ω resistor to R_IINSNS and a 10nF
ceramic capacitor to GND. A larger value capacitor to
GND may be used for additional filtering. Because the
input current sense amplifier gain is calibrated for 100Ω
filter resistors, any other filter resistance value will cause
an input current measurement error. The amplifier input
filter networks should be located as close to the V_{IN_SNS}
and I_{IN_SNS} pins as possible.
The capacitor from the intermediate bus to ground should
be a low ESR ceramic capacitor. It should be placed as
close as possible to the drain of the top gate MOSFET to
supply high frequency transient input current. This will
help prevent noise from the top gate MOSFET current
from feeding into the input current sense amplifier inputs
and supply.
If the input current sense amplifier is not used, short the
V_IN, V_{IN_SNS}, and I_{IN_SNS} pins together.
RCONFIG (External Resistor
Configuration Pins)
The LTC3883 default NVM is programmed to respect the
RCONFIG pins. If a user wishes the output voltage, PWM
frequency and phasing to be set without programming
the part or purchasing specially programmed parts, the
FREQ_CFG, VOUT_CFG, and VTRIM_CFG pins can be used
to establish these parameters. To save external components,
the user may float the FREQ_CFG, VOUT_CFG, and
VTRIM_CFG pins which will cause the LTC3883 to default
to the respective parameters stored in NVM. The ASEL pin
should always be programmed with a resistor divider to
safeguard against a lost device address by the host.
To externally program the RCONFIG pins connect a resistor
divider between the V_DD25 and GND of the LTC3883. The
RCONFIG pins are only monitored at initial power up and
during a reset so modifying their values perhaps using an
A/D after the part is powered will have no effect. 1% resis-
tors or better must be used to assure proper operation.
Noisy clock signals should not be routed near these pins.
Voltage Selection
When an output voltage is set using the RCONFIG pins
on VOUT_CFG and VTRIM_CFG, the following parameters
are set as a percentage of the output voltage:
• VOUT_OV_FAULT_LIMIT
+10%
• VOUT_OV_WARN_LIMIT
+7.5%
• VOUT_MAX
+7.5%
• VOUT_MARGIN_HIGH
+5%
• POWER_GOOD_ON
–7%
• POWER_GOOD_OFF
–8%
• VOUT_MARGIN_LOW
–5%
• VOUT_UV_WARN_LIMIT
–6.5%
• VOUT_UV_FAULT_LIMIT
–7%
Refer to Tables 12 and 13 to set the output voltage using
RCONFIG pins VOUT_CFG and VTRIM_CFG. RTOP is
connected between VDD25 and the pin and RBOTTOM is
connected between the pin and SGND. 1% resistors must
be used to assure proper operation.
The output voltage set point is equal to:
V_SETPOINT = VOUT_CFG + VTRIM_CFG
For example, if the VOUT_CFG pin has R_TOP equal to 24.9k
and R_BOTTOM equal to 4.32k, and VTRIM_CFG is set with
R_TOP not inserted and R_BOTTOM equal to 0Ω:
V_SETPOINT = 1.1V – 0.099V or 1.001V
If odd values of output voltage are required from 0.5V to
3.3V, use only the VOUT_CFG resistor divider, the V_TRIM
pin can be open or shorted to V_DD25. If the output set
point is 5V, the VOUT_CFG must have R_TOP equal to 10k
and R_BOTTOM equal to 23.2k and VTRIM_CFG must have
R_TOP equal to 20k and R_BOTTOM equal to 11k.
3883f
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