LTC3883 Datasheet, PDF (14/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Block Diagram
+^VIN
C_IN
R_IINSNS
R_VIN
V_{IN_SNS} I_{IN_SNS}
1
2
V_IN
28
C_VIN
+–
I_IN
19.5R 38R
R
R
PWM_CLOCK
S
RQ
I_CMP
3k
– ^IREV
+
I_LIM RANGE SELECT
HI: 1:1
LO: 1:1.5
+–
SLOPE
COMPENSATION
V_STBY
1.22V
REF
INTV_CC
UVLO
GND
I_TH
29
1
71.1k
ACTIVE
CLAMP
R_C
C_C1
33
GND
+
BURST
EA
+– +–
I_LIM DAC
(3 BITS)
UV
+–
OV
+–
0.56V
1Ω
5V REG
LTC3883
ONLY
INTV_CC/EXTV_CC (LTC3883-1)
27
3.3V
SUBREG
FCNT
ON
UV
REV
UVLO
SS
RUN
OV
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
16-BIT ⁺
ADC _–
8:1 ^{––++++––+}
MUX _–
+
2µA
30µA
–+–+–
PWM0
PWM1
V_DD33
21
BOOST ^DB
24
TG
C_B
23
SW
22
I_SENSE+
3
I_SENSE–
4
BG
26
C_INTVCC
25
PGND
R
AO
R
INTV_CC/EXTV_CC
V_DD33
M1
+
V_OUT
C_OUT
M2
R
31
V_SENSE–
R ^VSENSE+
30
TMUX
TSNS
32
9R
GND
2R
8-BIT
V_{IN_ON}
THRESHOLD DAC
12-BIT
SET POINT
DAC
SHARE_CLK 20
WP 19
SCL 6
SDA 7
ALERT 8
PMBus
INTERFACE
(400kHz
COMPATIBLE)
RUN 11
PGOOD 10
GPIO 9
CHANNEL
TIMING
MANAGEMENT
8-BIT
UV
DAC
8-BIT
OV
DAC
V_DD33
V_DD33
COMPARE
PHASE DET
V_CO
PHASE SELECTOR
CLOCK DIVIDER
GND
PWM
CLOCK
SLAVE
MISO
MAIN
CONTROL
CLK MOSI
MASTER
SINC³
UVLO
SYNC
PROGRAM
ROM
RAM
EEPROM
M2
V_DD33
GND
V_DD25
2.5V
SUBREG
5 SYNC
18 V_DD25
OSC
(32MHz)
CONFIG
DETECT
3883 F01
15 V_{OUT_CFG}
17 V_{TRIM_CFG}
14 FREQ_CFG
13 ASEL
Figure 1. Block Diagram
3883f
14