LTC3883 Datasheet, PDF (27/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
OPERATION
Responses To Input Overcurrent And Output
Undercurrent Faults
Input overcurrent and output undercurrent are measured
with the MUX’d ADC. Both of these measurements are
naturally deglitched by the 120ms typical response time
of the ADC. The fault responses are:
n _Ignore
n _{Shut Down Immediately—Latch Off}
n _{Shut Down Immediately—Retry Indefinitely at the Time}
Interval Specified in MFR_RETRY_DELAY
See Table 9.
Responses to External Faults
When the GPIO pin is pulled low, the OTHER bit is set in
the STATUS_WORD command, the appropriate bit is set
in the STATUS_MFR_SPECIFC command, and the ALERT
pin is pulled low. Responses are not deglitched. The
LTC3883 can be configured to ignore or shut down then
retry in response to its GPIO pin going low by modifying
the MFR_GPIO_RESPONSE command. To avoid the ALERT
pin asserting low when GPIO is pulled low, assert bit 1 of
MFR_CHAN_CONFIG_LTC3883.
Fault Logging
The LTC3883 has fault logging capability. Data is logged
into memory in the order shown in Table 11. The data is
stored in a continuously updated buffer in RAM. When
a fault event occurs, the fault log buffer is copied from
the RAM buffer into NVM. Fault logging is allowed at
temperatures above 85°C; however, retention of 10 years is
not guaranteed. When the die temperature exceeds 130°C,
the fault logging is delayed until the die temperature drops
below 120°C. The fault log data remains in NVM until a
MFR_FAULT_LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before
re-enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
When the LTC3883 powers-up, it checks the NVM for a
valid fault log. If a valid fault log exists in NVM, the “Valid
Fault Log” bit in the STATUS_MFR_SPECIFIC command
will be set and an ALERT event will be generated. Also,
fault logging will be blocked until the LTC3883 has
received a MFR_FAULT_LOG_CLEAR command before
fault logging will be re-enabled.
The information is stored in EEPROM in the event of any
fault that disables the controller. The GPIO pin being
externally pulled low will not trigger a fault logging event.
Bus Timeout Failure
The LTC3883 implements a timeout feature to avoid hang-
ing the serial interface. The data packet timer begins at the
first START event before the device address write byte.
Data packet information must be completed within 20ms or
the LTC3883 will three-state the bus and ignore the given
data packet. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), all data bytes and the PEC byte if applicable.
The LTC3883 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
applies primarily to the MFR_FAULT_LOG command. In
no circumstances will the timeout period be less than the
t_{TIMEOUT_SMB} specification of 32ms (typical).
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC3883
supports the full PMBus frequency range from 10kHz to
400kHz.
Similarity Between PMBus, SMBus and I²C
2-Wire Interface
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I²C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple
I²C byte commands because PMBus/SMBus provide
time-outs to prevent bus hangs and optional packet er-
ror checking (PEC) to ensure data integrity. In general, a
master device that can be configured for I²C communica-
tion can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
is not supported by all I²C controllers but is required for
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