LTC3883 Datasheet, PDF (56/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Applications Information
6. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the GND pin of the IC.
7. Are the V_{IN_SNS} and I_{IN_SNS} filters Kelvin connected
to the R_SENSEIN sense resistor? This will prevent the
PCB trace resistance from causing errors in the input
current measurement. These traces should be as short
as possible and routed away from any noisy nodes such
as the switching or boost nodes.
8. Is the V_IN filter Kelvin connected to the input side of
the R_SENSEIN resistor? This can help improve the noise
performance of the input current sense amplifier by
reducing the voltage transients between the amplifier
inputs and amplifier supply caused by the discontinuous
power stage current.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor the
current in the inductor while testing the circuit. Monitor the
output switching node (SW pin) to synchronize the oscil-
loscope to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the oper-
ating voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed cur-
rent level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce V_IN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering V_IN while
monitoring the outputs to verify operation.
56
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between C_IN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
Design Example
As a design example for a medium current regulator, as-
sume V_IN = 12V nominal, V_IN = 20V maximum, V_OUT =
3.3V, I_MAX = 15A and f = 500kHz (see Figure 28).
The regulated output is established by the VOUT_
COMMAND stored in NVM or placing the following resis-
tor divider between VDD25 the RCONFIG pin and SGND:
1. VOUT_CFG, R_TOP = 10k, R_BOTTOM = 15.8 k
2. VTRIM_CFG, Open
The frequency and phase are set by NVM or by setting
the resistor divider between VDD25 FREQ_CFG and GND
with R_TOP = 20k and R_BOTTOM = 12.7k. The address is set
to XF where X is the MSB stored in NVM.
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
n _{VOUT_OV_FAULT_LIMIT..................................... +10%}
n _{VOUT_OV_WARN_LIMIT................................... +7.5%}
n _{VOUT_MAX....................................................... +7.5%}
n _{VOUT_MARGIN_HIGH..........................................+5%}
n _{POWER_GOOD_ON..............................................–7%}
n _{POWER_GOOD_OFF.............................................–8%}
n _{VOUT_MARGIN_LOW...........................................–5%}
n _{VOUT_UV_WARN_LIMIT...................................–6.5%}
n _{VOUT_UV_FAULT_LIMIT.......................................–7%}
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