LTC3883 Datasheet, PDF (24/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Operation
MFR_RETRY_DELAY command and prevents damage
to the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
The GPIO pin of the LTC3883 can share faults with all
LTC PMBus products including the LTC3880, LTC2974,
LTC2978, LTC4676 µModule, etc. In the event of an internal
fault, one or more of the LTC3883s is configured to pull
the bussed GPIO pins low. The other LTC3883s are then
configured to shut down when the GPIO pin bus is pulled
low. For autonomous group retry, the faulted LTC3883
is configured to let go of the GPIO pin bus after a retry
interval, assuming the original fault has cleared. All the
LTC3883s in the group then begin a soft-start sequence.
If the fault response is LATCH_OFF, the GPIO pin remains
asserted low until either the RUN pin is toggled OFF/ON
or the part is commanded OFF/ON or the ARA command
operation is performed. The toggling of the RUN either by
the pin or OFF/ON command will clear faults associated
with the LTC3883. If it is desired to have all faults cleared
when either RUN pin is toggled, set bit 0 of MFR_
CONFIG_ALL_LTC3883 to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
CRC Failure
The integrity of the NVM memory is checked after a power-on
reset. A CRC failure will prevent the controller from leaving
the inactive state. If a CRC failure occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM repair
can be attempted by writing the desired configuration to the
controller and executing a STORE_USER_ALL command
followed by a CLEAR_FAULTS command.
The LTC3883 manufacturing section of the NVM is
mirrored. The NVM has the ability to perform limited repair
if either one of the two sections of the manufacturing
section of the NVM if the configuration becomes corrupted.
If a discrepancy is detected, the “NVM CRC Fault” in
the STATUS_MFR_SPECIFIC command is set. If this bit
24
remains set after being cleared by issuing a CLEAR_FAULTS
or writing a 1 to this bit, an irrecoverable internal fault has
occurred. The user is cautioned to disable both output
power supply rails associated with this specific part. There
are no provisions for field repairing unrecoverable NVM
faults in the manufacturing section.
Serial Interface
The LTC3883 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor divider. In addition the LTC3883
always responds to the global broadcast address of 0x5A
(7 bit) or 0x5B (7 bit).
The serial interface supports the following protocols defined
in the PMBus specifications: 1) send command, 2) write
byte, 3) write word, 4) group, 5) read byte, 6) read word
and 7) read block. All read operations will return a valid
PEC if the PMBus master requests it. If the PEC_REQUIRED
bit is set in the MFR_CONFIG_ALL_LTC3883 command,
the PMBus write operations will not be acted upon until
a valid PEC has been received by the LTC3883.
Communication Failure
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
Device Addressing
The LTC3883 offers four different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
Global addressing provides a means of the PMBus master
to address all LTC3883 devices on the bus. The LTC3883
global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and can-
not be disabled.
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTC3883. The value of the device address is set
3883f