LTC3883 Datasheet, PDF (63/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Applications Information
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.1, Part II, Section 10.8.7 and
SMBus v2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL_LTC3883. Clock
stretching will only occur if enabled and the bus com-
munication speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON command. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON (‘chip
not busy’). When the part is busy specifically because it
is in a transitional V_OUT state (margining hi/lo, power off/
on, moving to a new output voltage set point, etc.) it will
clear bit 4 of MFR_COMMON (‘output not in transition’).
When internal calculations are in process, the part will clear
bit 5 of MFR_COMMON (‘calculations not pending’). These
three status bits can be polled with a PMBus read byte of
the MFR_COMMON command until all three bits are set. A
command immediately following the status bits being set
will be accepted without NACKing or generating a BUSY
fault/ALERT notification. The part can NACK commands for
other reasons, however, as required by the PMBus spec
(for instance, an invalid command or data). An example
of a robust command write algorithm for the VOUT_
COMMAND register is provided in Figure 31.
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERTB notification. A simple way to achieve
this is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to
the application note TBD “Implementing Robust PMBus
System Software” located at www.linear.com/designtools/
app_notes.
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication without
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to en-
able clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.1,
Part II, Section 10.8.7 is required to communicate above
100kHz without clock stretching.
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