LTC3883 Datasheet, PDF (53/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
Applications Information
load current. When a load step occurs, V_OUT shifts by an
amount equal to ∆I_LOAD (ESR), where ESR is the effective
series resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return V_OUT to its steady-state value. During this recov-
ery time V_OUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
The availability of the I_TH pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed loop response. Assuming a predominantly
second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated
by examining the rise time at the pin. The I_TH external
components shown in the Typical Application circuit will
provide an adequate starting point for most applications.
The only two programmable parameters that affect loop
gain are the voltage range, bits 5 and 6 of the MFR_PWM_
CONFIG_LTC3883 command and the current range, bit 7
of the MFR_PWM_MODE_LTC3883 command. Be sure to
establish these settings prior to compensation calculation.
The I_TH series R_C-C_C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the
loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and I_TH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. Placing a power MOSFET with
a resistor to ground directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce to a load step. The MOSFET
+ R_SERIES will produce output currents approximately
equal to V_OUT/R_SERIES. R_SERIES values from 0.1Ω to 2Ω
are valid depending on the current limit settings and the
programmed output voltage. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I_TH pin signal which is in
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
creased by increasing R_C and the bandwidth of the loop
will be increased by decreasing C_C. If R_C is increased by
the same factor that C_C is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C_LOAD to C_OUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C_LOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PolyPhase Configuration
When configuring a PolyPhase rail with multiple LTC3883s/
LTC3880s, the user must share the SYNC, ITH, SHARE_
CLK, GPIO, and ALERT pins of both parts. Be sure to use
pull-up resistors on GPIO, SHARE_CLK and ALERT. One of
the part's SYNC pin must be set to the desired switching
frequency, and all other FREQUENCY_SWITCH commands
must be set to External Clock. If an external oscillator is
provided, set the FREQUENCY_SWITCH command to
External Clock for all parts. The relative phasing of all
the channels should be spaced equally. The MFR_RAIL_
ADDRESS of all the devices should be set to the same value.
When connecting a PolyPhase rail with LTC3883s, con-
nect the V_IN pins of the 3883s directly back to the supply
voltage through the V_IN pin filter networks. Refer to the
Typical Application circuit: High Efficiency 500kHz 2-Phase
1.8V Step-Down Converter with Sense Resistors.
3883f
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