LTC3883 Datasheet, PDF (28/112 Pages) Linear Technology – Single Phase Step-Down DC/DC Controller with Digital Power System Management

LTC3883/LTC3883-1
OPERATION
SMBus/PMBus reads. If a general purpose I²C controller
is used, check that repeat start is supported.
The LTC3883 supports the maximum SMBus clock
speed of 100kHz and is compatible with the higher speed
PMBus specification (between 100kHz and 400kHz) if
clock stretching is enabled. For robust communication and
operation refer to the Note section in the PMBus command
summary. Clock stretching is enabled by assserting bit 1
of MFR_CONFIG_ALL_LTC3883.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: Paragraph 5: Transport.
For a description of the differences between SMBus and
I²C, refer to System Management Bus (SMBus) Speci-
fication Version 2.0: Appendix B—Differences Between
SMBus and I²C.
PMBus Serial Digital Interface
The LTC3883 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 5, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC3883 is a slave device. The master can com-
municate with the LTC3883 using the following formats:
n _{Master transmitter, slave receiver}
n _{Master receiver, slave transmitter}
The following PMBus protocols are supported:
n _{Write Byte, Write Word, Send Byte}
n _{Read Byte, Read Word, Block Read}
n _{Alert Response Address}
Figures 7-16 illustrate the aforementioned PMBus proto-
cols. All transactions support PEC (parity error check) and
GCP (group command protocol). The Block Read supports
255 bytes of returned data. For this reason, the PMBus
timeout may be extended when reading the fault log.
Figure 6 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
1
7
11
8
11
S SLAVE ADDRESS Wr A DATA BYTE A P
x
x
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
... _{CONTINUATION OF PROTOCOL}
3883 F06
Figure 6. PMBus Packet Protocol Diagram Element Key
SDA
t_f
t_LOW
SCL
t_HD(STA)
START
CONDITION
t_r
t_SU(DAT)
t_f
t_HD(SDA)
t_HD(DAT)
t_HIGH
t_SU(STA)
REPEATED START
CONDITION
Figure 5. Timing Diagram
28
t_SP
t_r
t_BUF
t_SU(STO)
STOP
CONDITION
3883 F05
START
CONDITION
3883f