ISL6324A Datasheet, PDF (8/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 4)
MAX
TYP (Note 4) UNITS
UGATE Turn-On Non-overlap
t_PDHUGATE; V_PVCC = 12V, 3nF Load, Adaptive
10
ns
LGATE Turn-On Non-overlap
t_PDHLGATE; V_PVCC = 12V, 3nF Load, Adaptive
10
ns
GATE DRIVE RESISTANCE (Note 3)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
MODE SELECTION
V_PVCC = 12V, 15mA Source Current
V_PVCC = 12V, 15mA Sink Current
V_PVCC = 12V, 15mA Source Current
V_PVCC = 12V, 15mA Sink Current
2.0
Ω
1.65
Ω
1.25
Ω
0.80
Ω
VID1/SEL Input Low
EN taken from HI to LO, VDDIO = 1.5V
0.6
V
VID1/SEL Input High
EN taken from LO to HI, VDDIO = 1.5V
1.00
V
PVI INTERFACE
VIDx Pull-down
VDDIO = 1.5V
30
40
µA
VIDx Input Low
VDDIO = 1.5V
0.6
V
VIDx Input High
VDDIO = 1.5V
1.00
V
SVI INTERFACE
SVC, SVD Input LOW (VIL)
0.4
V
SVC, SVD Input HIGH (VIH)
0.95
V
Schmitt Trigger Input Hysteresis
0.14
0.35
0.45
V
SVD Low Level Output Voltage
3mA Sink Current
0.285
V
Maximum SVC, SVD Leakage (Note 3)
I²C INTERFACE
±5
µA
SCL, SDA Input LOW (VIL)
1.10
V
SCL, SDA Input HIGH (VIH)
1.75
V
Schmitt Trigger Input Hysteresis
0.18
0.35
0.50
V
SDA Low Level Output Voltage
3mA Sink Current
0.2
V
Maximum SCL, SDA Leakage (Note 3)
±5
µA
NOTES:
3. Limits should be considered typical and are not production tested.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
t_PDHUGATE
UGATE
LGATE
t_RUGATE
t_FUGATE
t_FLGATE
t_PDHLGATE
t_RLGATE
8
FN6880.1
April 29, 2010