ISL6324A Datasheet, PDF (10/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
ISEN1-, ISEN1+, ISEN2-, ISEN2+, ISEN3-, ISEN3+,
ISEN4-, and ISEN4+
These pins are used for differentially sensing the corresponding
channel output currents. The sensed currents are used for
channel balancing, protection, and core load line regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node
between the RC sense elements surrounding the inductor of
their respective channel. Tie the ISEN+ pins to the VCORE
side of their corresponding channel’s sense capacitor.
UGATE1 and UGATE2
Connect these pins to the corresponding upper MOSFET
gates. These pins are used to control the upper MOSFETs
and are monitored for shoot-through prevention purposes.
Maximum individual channel duty cycle is limited to 93.3%.
BOOT1 and BOOT2
These pins provide the bias voltage for the corresponding
upper MOSFET drives. Connect these pins to appropriately
chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC1_2 pin provide the
necessary bootstrap charge.
PHASE1 and PHASE2
Connect these pins to the sources of the corresponding
upper MOSFETs. These pins are the return path for the
upper MOSFET drives.
LGATE1 and LGATE2
These pins are used to control the lower MOSFETs. Connect
these pins to the corresponding lower MOSFETs’ gates.
PWM3 and PWM4
Pulse-width modulation outputs. Connect these pins to the
PWM input pins of an Intersil driver IC if 3- or 4-phase
operation is desired. Connect the ISEN- pins of the channels
not desired to +5V to disable them and configure the core
VR controller for 2-phase or 3-phase operation.
PWROK
System wide Power Good signal. If this pin is low, the two
SVI bits are decoded to determine the “metal VID”. When the
pin is high, the SVI is actively running its protocol.
RSET
Connect this pin to the VCC pin through a resistor (R_SET) to
set the effective value of the internal R_ISEN current sense
resistors. The values of the R_SET resistor should be no less
than 20kΩ and no more than 80kΩ. A 0.1µF capacitor
should be placed in parallel to the R_SET resistor.
VDDPWRGD
During normal operation this pin indicates whether both output
voltages are within specified overvoltage and undervoltage
limits. If either output voltage exceeds these limits or a reset
event occurs (such as an overcurrent event), the pin is pulled
low. This pin is always low prior to the end of soft-start.
DVC
The DVC pin is a buffered version of the reference to the error
amplifier. A series resistor and capacitor between the DVC pin
and FB pin smooth the voltage transition during VID-on-the-fly
operations.
FB_NB and COMP_NB
These pins are the internal error amplifier inverting input and
output respectively of the NB VR controller. FB_NB,
VDIFF_NB, and COMP_NB are tied together through
external R-C networks to compensate the regulator.
ISEN_NB-, ISEN_NB+
These pins are used for differentially sensing the North
Bridge output current. The sensed current is used for
protection and load line regulation if droop is enabled.
Connect ISEN_NB- to the node between the RC sense
element surrounding the inductor. Tie the ISEN_NB+ pin to
the VNB side of the sense capacitor.
UGATE_NB
Connect this pin to the corresponding upper MOSFET gate.
This pin provides the PWM-controlled gate drive for the
upper MOSFET and is monitored for shoot-through
prevention purposes.
BOOT_NB
This pin provides the bias voltage for the corresponding
upper MOSFET drive. Connect this pin to appropriately
chosen external bootstrap capacitor. The internal bootstrap
diode connected to the PVCC_NB pin provides the
necessary bootstrap charge.
PHASE_NB
Connect this pin to the source of the corresponding upper
MOSFET. This pin is the return path for the upper MOSFET
drive. This pin is used to monitor the voltage drop across the
upper MOSFET for overcurrent protection.
LGATE_NB
Connect this pin to the corresponding MOSFET’s gate. This
pin provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
SCL
Connect this pin to the clock signal for the I²C bus, which is
a logic level input signal. The clock signal tells the controller
when data is available on the I²C bus.
SDA
Connect this pin to the bidirectional data line of the I²C bus,
which is a logic level input/output signal. All I²C data is sent
over this line, including the address of the device the bus is
trying to communicate with, and what functions the device
should perform.
10
FN6880.1
April 29, 2010