ISL6324A Datasheet, PDF (25/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
ISL6324A I²C Slave Address
All devices on the I²C bus must have a 7-Bit I²C address in
order to be recognized. The address for the ISL6324A is
1000_110.
Communicating Over the I²C Bus
Two transactions are supported on the I²C interface:
1. Write register
2. Read register from current address.
All transactions start with a control byte sent from the I²C
master device. The control byte begins with a Start condition,
followed by 7-Bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write or 1 for a read. If
any slaves on the I²C bus recognize their address, they will
Acknowledge by pulling the serial data line low for the last
clock cycle in the control byte. If no slaves exist at that
address or are not ready to communicate, the data line will
be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL6324A
acknowledges it, the 2nd byte sent by the master must be a
register address byte. This register address byte tells the
ISL6324A which one of the internal registers it wants to write
to or read from. The address of the first internal register,
RGS1, is 0000_0000. This register sets the North Bridge
Offset, Overvoltage trip point and Power-good trip level. The
address of the second internal register, RGS2, is 0000_0001.
This register sets the Core Offset, Overvoltage trip point and
Power-good trip level. The address of the third register,
RGS3, is 0000_0010. The third register is for programming of
the Power Savings Mode features. Once the ISL6324A
receives a correct register address byte, it responds with an
acknowledge.
TABLE 5. I2C REGISTER FUNCTIONS
REGISTER ADDRESS
FUNCTION
RGS1 0000_0000 North Bridge DAC Offset, OVP, PGOOD
RGS2 0000_0001 Core DAC Offset, OVP, PGOOD
RGS3 0000_0010 Power Savings Mode Functionality
Writing to the Internal Registers
In order to change any of the three operating parameters via
the I²C bus, the internal registers must be written to. The two
registers inside the ISL6324A can be written individually with
two separate write transactions or sequentially with one write
transaction by sending two data bytes. See “Reading from
the Internal Registers” on page 25.
To write to a single register in the ISL6324A, the master
sends a control byte with the R/W bit set to 0, indicating a
write. If it receives an Acknowledge from the ISL6324A, it
sends a register address byte representing the internal
register it wants to write to (0000_0000 for RGS1,
0000_0001 for RGS2 or 0000_0010 for RGS3). The
ISL6324A will respond with an Acknowledge. The master
then sends a byte representing the data byte to be written
into the desired register. The ISL6324A will respond with an
Acknowledge. The master then issues a Stop condition,
indicating to the ISL6324A that the current transaction is
complete. Once this transaction completes, the ISL6324A
will immediately update and change the operating
parameters on-the-fly.
It is also possible to write to the all the registers sequentially.
To do this the master must write to register RGS1first. This
transaction begins with the master sending a control byte
with the R/W bit set to 0. If it receives an Acknowledge from
the ISL6324A, it sends the register address byte 0000_0000,
representing the internal register RGS1. The ISL6324A will
respond with an Acknowledge. After sending the data byte to
RGS1 and receiving an Acknowledge from the ISL6324A,
instead of sending a Stop condition, the master sends the
data byte to be stored in register RGS2. After the ISL6324A
responds with another Acknowledge, the master can either
send a Stop condition to indicate that the current transaction
is complete, or it can send the data byte to be stored in
register RGS3. If register RGS3 is written to, the ISL6324A
will respond with an Acknowledge and the master would
send a Stop condition, completing the transaction. Once this
transaction completes the ISL6324A will immediately update
and change the operating parameters on-the-fly.
Reading from the Internal Registers
The ISL6324A has the ability to read from both registers
separately or read from them consecutively. Prior to reading
from an internal register, the master must first select the
desired register by writing to it and sending the register’s
address byte. This process begins by the master sending a
control byte with the R/W bit set to 0, indicating a write. Once
it receives an Acknowledge from the ISL6324A, it sends a
register address byte representing the internal register it
wants to read from (0000_0000 for RGS1, 0000_0001 for
RGS2 or 0000_0010 for RGS3). The ISL6324A will respond
with an Acknowledge. The master must then respond with a
Stop condition. After the Stop condition, the master follows
with a new Start condition, and then sends a new control
byte with the R/W bit set to 1, indicating a read. The
ISL6324A will then respond by sending the master an
Acknowledge, followed by the data byte stored in that
register. The master must then send a Not Acknowledge
followed by a Stop command, which will complete the read
transaction.
It is also possible for all registers to be read consecutively.
To do this the master must read from register RGS1 first.
This transaction begins with the master sending a control
byte with the R/W bit set to 0. If it receives an Acknowledge
from the ISL6324A, it sends the register address byte
0000_0000, representing the internal register RGS1. The
ISL6324A will respond with an Acknowledge. The master
must then respond with a Stop condition. After the Stop
condition the master follows with a new Start condition, and
25
FN6880.1
April 29, 2010