ISL6324A Datasheet, PDF (36/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
3-phase and two-phase designs respectively. Use the same
approach for selecting the bulk capacitor type and number.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET
turn on and off. Select low ESL ceramic capacitors and place
one as close as possible to each upper MOSFET drain to
minimize board parasitics and maximize suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with which
the current transitions from one device to another causes
voltage spikes across the interconnecting impedances and
parasitic circuit elements. These voltage spikes can degrade
efficiency, radiate noise into the circuit and lead to device
overvoltage stress. Careful component selection, layout, and
placement minimizes these voltage spikes. Consider, as an
example, the turnoff transition of the upper PWM MOSFET.
Prior to turnoff, the upper MOSFET was carrying channel
current. During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET. Any
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short, wide
circuit traces minimize the magnitude of voltage spikes.
0.3
I_L(P-P) = 0
I_L(P-P) = 0.25 I_O
I_L(P-P) = 0.5 I_O
I_L(P-P)= 0.75 I_O
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_IN/V_O)
FIGURE 27. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
0.3
0.2
0.1
I_L(P-P) = 0
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_IN/V_O)
FIGURE 28. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
There are two sets of critical components in a DC/DC converter
using a ISL6324A controller. The power components are the
most critical because they switch large amounts of energy. Next
are small signal components that connect to sensitive nodes or
supply critical bypassing current and signal coupling.
The power components should be placed first, which include
the MOSFETs, input and output capacitors, and the inductors. It
is important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally
across all power trains. Equidistant placement of the controller
to the CORE and NB power trains it controls through the
integrated drivers helps keep the gate drive traces equally
short, resulting in equal trace impedances and similar drive
capability of all sets of MOSFETs.
When placing the MOSFETs try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally
possible. Input high-frequency capacitors, C_HF, should be
placed close to the drain of the upper FETs and the source of
the lower FETs. Input bulk capacitors, CBULK, case size
typically limits following the same rule as the high-frequency
input capacitors. Place the input bulk capacitors as close to the
drain of the upper FETs as possible and minimize the distance
to the source of the lower FETs.
Locate the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency output decoupling
capacitors (ceramic) should be placed as close as practicable
to the decoupling target, making use of the shortest connection
paths to any internal planes, such as vias to GND next or on the
capacitor solder pad.
36
FN6880.1
April 29, 2010