ISL6324A Datasheet, PDF (3/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
Controller Block Diagram
FB_NB
COMP_NB
NB_OVP
SCL
CORE_OVP
I²C
SDA
DAC_OFS
E/A
ISEN_NB+
ISEN_NB-
CURRENT
UV
SENSE LOGIC
OV
LOGIC
NB_REF
RAMP
MOSFET
DRIVER
VDDPWRGD
APA
COMP
FB
DVC
RGND
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
VID5
VSEN
RSET
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
APA
NB
FAULT
LOGIC
EN_12V
ENABLE
LOGIC
VDDPWRGD_MOD
E/A
2X
SOFT-START
AND
FAULT LOGIC
∑
SVI
SLAVE
BUS
AND
PVI
DAC
DAC_OFS
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
DROOP
CONTROL
NB_REF
OV
LOGIC
CORE_OVP
∑
∑
UV
LOGIC
RESISTOR
MATCHING
CH1
CURRENT
SENSE
∑
OC
∑
I_TRIP I_AVG
CH2
CURRENT
SENSE
CH3
CURRENT
SENSE
ISEN3-
CH4
CURRENT
SENSE
ISEN4-
CHANNEL
CURRENT
BALANCE
I_AVG ₁
N
∑
PWM1
PWM2
PWM3
PWM4
GND
POWER-ON
RESET
MOSFET
DRIVER
MOSFET
DRIVER
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN3-
ISEN4-
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
PVCC_NB
EN
VCC
PVCC1_2
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
3
FN6880.1
April 29, 2010