ISL6324A Datasheet, PDF (7/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
Electrical Specifications Recommended Operating Conditions (0°C to +70°C), Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 4) TYP
System Accuracy (0.600V < VDAC < 1.000V)
-1.0
System Accuracy (VDAC < 0.600V)
-2.0
DVC Voltage Gain
VDAC = 1V
2.0
APA Current Tolerance
ERROR AMPLIFIER
V_APA = 1V
90
100
DC Gain
Gain-Bandwidth Product (Note 3)
Slew Rate (Note 3)
Maximum Output Voltage
R_L = 10k to ground, (Note 3)
C_L = 100pF, R_L = 10k to ground, (Note 3)
C_L = 100pF, Load = ±400µA, (Note 3)
Load = 1mA
96
20
8
3.80
4.20
Minimum Output Voltage
Load = -1mA
1.3
SOFT-START RAMP
Soft-Start Ramp Rate
2.2
3.0
PWM OUTPUTS
PWM Output Voltage LOW Threshold
I_LOAD = ±500µA
PWM Output Voltage HIGH Threshold
I_LOAD = ±500µA
4.5
CURRENT SENSING - CORE CONTROLLER
Sensed Current Tolerance
V_ISENn- - V_ISENn+ = 23.2mV, R_SET = 37.6kΩ,
68
4 Phases, T_A = +25°C
CURRENT SENSING - NB CONTROLLER
Sensed Current Tolerance
DROOP CURRENT
V_{ISEN_NB-} - V_{ISEN_NB+} = 23.2mV,
68
R_SET = 37.6kΩ, 4 Phases, T_A = +25°C
Tolerance
OVERCURRENT PROTECTION
V_ISENn- - V_ISENn+ = 23.2mV, R_SET = 37.6kΩ,
68
4 Phases, T_A = +25°C
Overcurrent Trip Level - Average Channel
Normal Operation, R_SET = 28.2kΩ
Dynamic VID Change (Note 3)
87
100
130
Overcurrent Limiting- Individual Channel
Normal Operation, R_SET = 28.2kΩ
142
Dynamic VID Change (Note 3)
190
POWER-GOOD
Core Overvoltage Threshold
VSEN Rising
Bit 6 of I²C data = 0
VDAC + VDAC +
225mV 250mV
Undervoltage Threshold
VSEN Falling (Core)
Bit 6 of I²C data = 0
VDAC - VDAC -
325mV 300mV
ISEN_NB+ Falling (North Bridge)
Bit 6 of I²C data = 0
VDAC - VDAC -
310mV 275mV
Power Good Hysteresis
50
OVERVOLTAGE PROTECTION
OVP Trip Level
Bit 7 of I²C data = 0, VDAC ≤ 1.55V
1.73
1.80
OVP Lower Gate Release Threshold
350
400
SWITCHING TIME (Note 3) [See “Timing Diagram” on page 8]
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
t_RUGATE; V_PVCC = 12V, 3nF Load, 10% to 90%
26
t_RLGATE; V_PVCC = 12V, 3nF Load, 10% to 90%
18
t_FUGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
18
t_FLGATE; V_PVCC = 12V, 3nF Load, 90% to 10%
12
MAX
(Note 4)
1.0
2.0
108
1.6
4.0
0.5
88
89
88
120
VDAC +
275mV
VDAC -
270mV
VDAC -
235mV
1.84
UNITS
%
%
V
µA
dB
MHz
V/µs
V
V
mV/µs
V
V
µA
µA
µA
µA
µA
µA
µA
V
mV
mV
mV
V
mV
ns
ns
ns
ns
7
FN6880.1
April 29, 2010