ISL6324A Datasheet, PDF (30/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 26
and 27, respectively.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
(EQ. 26)
P _{Q g _Q1}
=
3_--
2
⋅
Q_G1
⋅
PVCC
⋅
f_SW
⋅
N_Q1
⋅
N_PHASE
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ f_SW ⋅ N_Q2 ⋅ N_PHASE
I_DR
=
⎛
⎝
3_--
2
⋅
Q_G1
⋅
N_Q
1
+
Q_G
2
⋅
N_Q
⎞
2⎠
⋅ N_PHASE ⋅ f_SW + I_Q
(EQ. 27)
In Equations 26 and 27, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power
loss; the gate charge (Q_G1 and Q_G2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I_Q is the driver total
quiescent current with no load at both drive outputs; N_Q1 and
N_Q2 are the number of upper and lower MOSFETs per phase,
respectively; N_PHASE is the number of active phases. The
I_Q*VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
PVCC
BOOT
R_HI1
R_LO1
PHASE
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance (P_{DR_UP}) the lower drive path resistance
(P_{DR_UP}) and in the boot strap diode (P_BOOT). The rest of
the power will be dissipated by the external gate resistors
(R_G1 and R_G2) and the internal gate resistors (R_GI1 and
R_GI2) of the MOSFETs. Figures 19 and 20 show the typical
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, P_DR, can be roughly
estimated as Equation 28:
P_DR = P_{DR_UP} + P_{DR_LOW} + P_BOOT + (I_Q ⋅ VCC)
P_BOOT
=
-^P----^Q----^g----^_--^Q-----¹-
3
(EQ. 28)
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
R^-----_L^---_O^-----₁^{R----+-L---O-}R^----1-_E^----_X^----_T^---₁^- _{⎠⎟⎞}
⋅ ^P-----^Q----^g----^_--^Q-----¹-
3
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
⋅ ^P-----^Q----^g----^_--^Q-----²-
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
Inductor DCR Current Sensing Component
Selection and R_SET Value Calculation
With the single R_SET resistor setting the value of the
effective internal sense resistors for both the North Bridge
and Core regulators, it is important to set the R_SET value
and the inductor RC filter gain, K, properly. See “Continuous
Current Sampling” on page 13 and “Channel-Current
Balance” on page 14 for more details on the application of
the R_SET resistor and the RC filter gain.
There are 3 separate cases to consider when calculating
these component values. If the system under design will
never utilize the North Bridge regulator and the ISL6323 will
always be in parallel mode, then follow the instructions for
Case 3 and only calculate values for Core regulator
components.
For all three cases, use the expected VID voltage that would
be used at TDC for Core and North Bridge for the V_CORE
and V_NB variables, respectively.
CASE 1
I_NBM
A
X
⋅
D
C
R
N
B
<
I_{--C-----o---r--e---M-----A----X--}
N
⋅
DC
R_Co
r
e
(EQ. 29)
In Case 1, the DC voltage across the North Bridge inductor
at full load is less than the DC voltage across a single phase
of the Core regulator while at full load. Here, the DC voltage
across the Core inductors must be scaled down to match the
DC voltage across the North Bridge inductor, which will be
impressed across the ISEN_NB pins without any gain. Thus,
30
FN6880.1
April 29, 2010