ISL6324A Datasheet, PDF (12/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1μs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
Active Pulse Positioning Modulated PWM Operation
The ISL6324A uses a proprietary Active Pulse Positioning
(APP) modulation scheme to control the internal PWM signals
that command each channel’s driver to turn their upper and
lower MOSFETs on and off. The time interval in which a PWM
signal can occur is generated by an internal clock, whose cycle
time is the inverse of the switching frequency set by the resistor
between the FS pin and ground. The advantage of Intersil’s
proprietary Active Pulse Positioning (APP) modulator is that the
PWM signal has the ability to turn on at any point during this
PWM time interval, and turn off immediately after the PWM
signal has transitioned high. This is important because it allows
the controller to quickly respond to output voltage drops
associated with current load spikes, while avoiding the ring
back affects associated with other modulation schemes.
The PWM output state is driven by the position of the error
amplifier output signal, V_COMP, minus the current correction
signal relative to the proprietary modulator ramp waveform as
illustrated in Figure 3. At the beginning of each PWM time
interval, this modified V_COMP signal is compared to the
internal modulator waveform. As long as the modified V_COMP
voltage is lower then the modulator waveform voltage, the
PWM signal is commanded low. The internal MOSFET driver
detects the low state of the PWM signal and turns off the
upper MOSFET and turns on the lower synchronous
MOSFET. When the modified V_COMP voltage crosses the
modulator ramp, the PWM output transitions high, turning off
the synchronous MOSFET and turning on the upper
MOSFET. The PWM signal will remain high until the modified
V_COMP voltage crosses the modulator ramp again. When this
occurs the PWM signal will transition low again.
During each PWM time interval the PWM signal can only
transition high once. Once PWM transitions high it can not
transition high again until the beginning of the next PWM
time interval. This prevents the occurrence of double PWM
pulses occurring during a single period.
To further improve the transient response, ISL6324A also
implements Intersil’s proprietary Adaptive Phase Alignment
(APA) technique, which turns on all phases together under
transient events with large step current. With both APP and
APA control, ISL6324A can achieve excellent transient
performance and reduce the demand on the output capacitors.
Adaptive Phase Alignment (APA)
To further improve the transient response, the ISL6324A
also implements Intersil’s proprietary Adaptive Phase
Alignment (APA) technique, which turns on all of the
channels together at the same time during large current step
transient events. As Figure 3 shows, the APA circuitry works
by monitoring the voltage on the APA pin and comparing it to
a filtered copy of the voltage on the COMP pin. The voltage
on the APA pin is a copy of the COMP pin voltage that has
been negatively offset. If the APA pin exceeds the filtered
COMP pin voltage an APA event occurs and all of the
channels are forced on.
EXTERNAL CIRCUIT
APA
ISL6324A INTERNAL CIRCUIT
C_APA
R_{APA VAPA,TRIP}
COMP
100µA
LOW
PASS
FILTER
+
APA
-
TO APA
CIRCUITRY
ERROR
AMPLIFIER
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion
that the APA and COMP pins must have during a transient
event to activate the Adaptive Phase Alignment circuitry.
This APA trip level is set through a resistor, R_APA, that
connects from the APA pin to the COMP pin. A 100µA
current flows across R_APA into the APA pin to set the APA
trip level as described in Equation 4. An APA trip level of
500mV is recommended for most applications. A 0.1µF
capacitor, C_APA, should also be placed across the R_APA
resistor to help with noise immunity.
V_{APA, TRIP} = R_APA ⋅ 100 × 10^–6
(EQ. 4)
PWM Operation
The timing of each core channel is set by the number of
active channels. Channel detection on the ISEN2-, ISEN3-
and ISEN4- pins selects 1-Channel to 4-Channel operation
for the ISL6323A. The switching cycle is defined as the time
between PWM pulse termination signals of each channel.
The cycle time of the pulse signal is the inverse of the
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FN6880.1
April 29, 2010