ISL6324A Datasheet, PDF (24/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
parameters and programmability of the Power Savings Mode
feature. The parameters that can be adjusted through the
I²C are:
1. Voltage Margining Offset: The DAC voltage can be
offset in 25mV increments.
2. VDDPWRGD Trip Level: The PGOOD trip level for either
the Core regulator or the North Bridge regulator can be
increased.
3. Overvoltage Trip Level: The OVP trip level of either the
Core or North Bridge regulator can be increased.
4. Power Savings Mode Options:
a. The number of phases to drop to in Power Savings
Mode can be programmed
b. The number of PWM cycles between dropping phases
while entering Power Savings Mode can be
programmed.
c. The number of PWM cycles between adding phases
when exiting Power Savings Mode can be
programmed.
d. Core Voltage Margining Offset can be Enabled or
Disabled while in Power Savings Mode.
To adjust these parameters, data transmission from the main
microprocessor to the ISL6324A and vice versa must take
place through the two wire I²C bus interface. The two wires of
the I²C bus consist of the SDA line, over which all data is sent,
and the SCL line, which is a clock signal used to synchronize
sending/receiving of the data.
Both SDA and SCL are bidirectional lines, externally connected
to a positive supply voltage via a pull-up resistor. Pull-up
resistor values should be chosen to limit the input current to
less then 3mA. When the bus is free, both lines are HIGH. The
output stages of ISL6324A have an open drain/open collector in
order to perform the wired-AND function. Data on the I²C bus
can be transferred up to 100Kbps in the standard-mode or up to
400Kbps in the fast-mode. The level of logic “0” and logic “1” is
dependent on associated value of V_DD as per electrical
specification table. One clock pulse is generated for each data
bit transferred. The ISL6324A is a “SLAVE only” device, so the
SCL line must always be controlled by an external master.
It is important to note that the I²C interface of the ISL6324A
only works once the voltage on the VCC pin has risen above
the POR rising threshold. The I²C will continue to remain
active until the voltage on the VCC pin falls back below the
falling POR threshold level.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW. Refer
to Figure 15.
SDA
SCL
DATA LINE CHANGE
STABLE OF DATA
DATA VALID ALLOWED
FIGURE 15. DATA VALIDITY
START and STOP Conditions
Figure 16 shows a START (S) condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition..
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
FIGURE 16. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB) and the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9-clock pulses.
The ninth pulse is the acknowledge bit (A). After the start
condition, the master sends 7 slave address bits and a R/W
bit during the next 8-clock pulses. During the ninth clock
pulse, the device that recognizes its own address holds the
data line low to acknowledge. The acknowledge bit is also
used by both the master and the slave to acknowledge
receipt of register addresses and data as described in
Figure 17.
SCL
1
2
8
9
SDA
START
MSB
ACKNOWLEDGE
FROM SLAVE
FIGURE 17. ACKNOWLEDGE ON THE I²C BUS
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FN6880.1
April 29, 2010