ISL6324A Datasheet, PDF (1/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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Data Sheet
ISL6324A
Hybrid SVI/PVI with I²C
April 29, 2010
FN6880.1
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6324A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6324A supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6324A features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is provided
by a 2-to-4-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers, adding flexibility in
layout, reduce the number of external components in the multi-
phase section. A single phase PWM controller with integrated
driver provides a second precision voltage regulation system
for the North Bridge portion of the processor. This monolithic,
dual controller with integrated driver solution provides a cost
and space saving power management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6324A features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient response
to load application and removal. One of these features is
highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6324A supports Power Savings Mode by dropping
phases when the PSI_L bit is set. The number of phases
that the ISL6324A will drop to is programmable through an
I²C interface. The number of PWM cycles between both
dropping phases when entering Power Savings Mode and
adding phases when exiting Power Savings Mode is also
programmable through the I²C interface.
The ISL6324A I²C interface also allows independent
programmable output voltage offset for both the Core and
North Bridge regulators. The I²C interface can also be used
to set the PGOOD and OVP trip levels for both regulators as
well.
Features
Processor Core Voltage Regulator Features
• Configuration Flexibility
- 1- or 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• Parallel VID (6-bit) Interface Inputs for PVI Mode
• PSI_L Support via Phase Shedding
• Differential Remote Voltage Sensing
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
Processor Core Voltage Regulator and North Bridge
Voltage Regulator Shared Features
• Precision Voltage Regulation: ±0.5% System Accuracy
Over-Temperature
• Two Wire, AMD Compliant Serial VID Interface Inputs for
SVI Mode
• I²C Interface
- Voltage Margining, OVP and PGOOD Trip Levels
- Enhanced PSI_L State Control
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing for Core
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6324ACRZ* ISL6324A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6324AIRZ* ISL6324A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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