ISL6324A Datasheet, PDF (19/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, the
average current of all active channels, I_AVG, flows from FB
through a load-line regulation resistor R_FB. The resulting
voltage drop across R_FB is proportional to the output current,
effectively creating an output voltage droop with a
steady-state value defined as in Equation 12:
V_DROOP = I_AVG ⋅ R_FB
(EQ. 12)
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
shown in Equation 13.
V_OUT
=
V_REF
–
⎛
⎜
⎝
-^I-^O-----^U----^T--
N
⋅
DCR
⋅
⎛
⎝
4_----0_---0_--
3
⋅
R^-----_S^--1--_E^----_T^{- ⎠⎞}
⋅K⋅
⎞
R _{F B⎠⎟}
(EQ. 13)
In Equation 13, V_REF is the reference voltage, I_OUT is the
total output current of the converter, K is the DC gain of the
RC filter across the inductor (K is defined in Equation 7), N is
the number of active channels, and DCR is the Inductor
DCR value.
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6324A through
either the PVI or SVI interface. The ISL6324A manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6324A begins slewing the
DAC at 3.25mV/µs until the DAC and target voltage are
equal. Thus, the total time required for a dynamic VID
transition is dependent only on the size of the DAC change.
To further improve dynamic VID performance, ISL6324A
also implements a proprietary DAC smoothing feature. The
external series RC components connected between DVC
and FB limit any stair-stepping of the output voltage during a
VID-on-the-Fly transition.
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, R_FB, and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
VSEN
R_FB ^IDVC ^{= I}C
I_C
I_DVC
C_DVC
DVC
R_DVC
C_C
FB
R_C
COMP
VDAC+RGND
-
+ _ERROR
AMPLIFIER
ISL6324A INTERNAL CIRCUIT
FIGURE 9. DYNAMIC VID COMPENSATION NETWORK
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
and capacitor in series, R_DVC and C_DVC, between the DVC
and the FB pin.
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
ISL6324A sets the voltage on the DVC pin to be 2x the
voltage on the REF pin. Since the error amplifier forces the
voltage on the FB pin and the REF pin to be equal, the
resulting voltage across the series RC between DVC and FB
is equal to the REF pin voltage. The RC compensation
components, R_DVC and C_DVC, can then be selected to
create the desired amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier RC components, R_C and C_C, that are in series
between the FB and COMP pins. Use Equations 14, 15 and
16 to calculate the RC component values, R_DVC and C_DVC,
for the VID-on-the-fly compensation network. For these
equations: V_IN is the input voltage for the power train; V_P-P
is the oscillator ramp amplitude (1.5V); and R_C and C_C are
the error amplifier RC components between the FB and
COMP pins.
A
=
-----^K-----¹------
K1 – 1
(EQ. 14)
K1
=
----^V----^I--^N-----
V_{P – P}
R_RCOMP = A × R_C
C_RCOMP
=
C_-----C--
A
(EQ. 15)
(EQ. 16)
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
19
FN6880.1
April 29, 2010