ISL6324A Datasheet, PDF (34/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
ISL6324A
VSEN
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
.
R₁
=
R_FB
⋅ ------------C------^â‹---E----S-----R-------------
L ⋅ C – C ⋅ ESR
(EQ. 50)
C₁
=
-----L-----^â‹---C-----^–-----C------^â‹---E----S-----R--
R_FB
C₂
=
----------------------------------------0---.--7---5-----^â‹---V-----^I-^N------------------------------------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_{P – P}
R_C
=
-V----^P----^P-----^â‹---^⎝⎛---2----^π---^⎠⎞---²-----^â‹---f--⁰----^â‹---f--^H----^F-----^â‹---L-----^â‹---C-----^â‹---R-----^F----^B--
0.75 ^⋠V_IN ^{⋅ (2 ⋅ π ⋅ f}_HF ^{⋅ L ⋅ C–1)}
C_C
=
---------0---.--7---5-----^â‹---V----^I--^N------^â‹---⁽--2-----^â‹---^π-----^â‹---f--^H----^F----^â‹--------L-----^â‹--C-----^–----1---⁾---------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_{P – P}
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 51, R_FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 51.
In Equation 51, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_P-P is the peak-to-
peak sawtooth signal amplitude as described in “Electrical
Specifications” on page 6.
Output Filter Design
Case 1:
---------------1----------------
2⋅π⋅ L⋅C
>
f₀
R_C
=
R_FB
⋅
2-----⋅_---π_-----⋅_---f--0----⋅_{---V-----P------P-----}⋅_{-------L-----}⋅_---C---
0.66 ⋅ V_IN
C_C = _2-----â‹---_π-----_â‹--0-V--.--6_P---6-_---_P--^â‹---_â‹^V---R-I--^N-_F----_B-----_â‹---f--₀-
Case 2:
---------------1----------------
2⋅π⋅ L⋅C
≤
f₀
<
------------------1-------------------
2 ⋅ π ⋅ C ⋅ ESR
R_C = R_FB ⋅ ^V-----P---^---^P-----^â‹---⁽--02---.--6^â‹---^π_6----⁾-_â‹-²----V-^â‹---_I-f-_N-⁰--²----^â‹----L-----^â‹---C--
C_C
=
-------------------------------0---.--6---6-----^â‹---V-----^I-^N---------------------------------
(2 ⋅ π)² ⋅ f₀₂ ⋅ V_P-P ⋅ R_FB ⋅ L ⋅ C
(EQ. 51)
Case 3:
f₀ > _2-----â‹---_π-----_â‹---C--1----_â‹---E----S-----R---
R_C
=
R_FB
⋅
2-----⋅_---π_------⋅_---f--0----⋅_{---V----P-------P-----}⋅_---L-
0.66 ⋅ V_IN ⋅ ESR
C_C
=
-----0----.-6----6----^â‹---V-----^I-^N------^â‹---E----S-----R-----^â‹--------C-------
2 ⋅ π ⋅ V_P-P ⋅ R_FB ⋅ f₀ ⋅ L
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
as shown in Equation 52:
ΔV
≈
ESL
⋅
-d---i
dt
+
ESR
⋅
ΔI
(EQ. 52)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
34
FN6880.1
April 29, 2010