ISL6324A Datasheet, PDF (35/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 11 and Equation 3), a voltage develops across the bulk
capacitor ESR equal to I_{C(P-P )} (ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, V_P-P(MAX), determines the lower limit on the
inductance.
L
≥ ESR ⋅
⎝⎛ ^{V I N}
–
N
⋅
V_O
U
⎞
T_⎠
⋅
V_OUT
-------------------------------------------------------------------
f_S ⋅ V_IN ⋅ V_{P – P(MAX)}
(EQ. 53)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 54 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 55
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
2 ⋅ N ⋅ C ⋅ V_O
L
≤
---------------------------------
(ΔI)²
⋅
ΔV_MAX – (ΔI ⋅ ESR)
(EQ. 54)
L
≤
-1---.--2---5-----^â‹---N------^â‹---C--
(ΔI)²
⋅
ΔV_MAX – (ΔI ⋅ ESR)
⋅ _⎝⎛V_IN – V_{O⎠⎞}
(EQ. 55)
Switching Frequency
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
“MOSFETs” on page 28, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small output-
voltage ripple as outlined in “Output Filter Design” on page 34.
Choose the lowest switching frequency that allows the
regulator to meet the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R_T. Figure 25 and Equation 56
are provided to assist in selecting the correct value for R_T.
RT
=
[10.61
10
–
(1.035
⋅
log (fS))]
1k
(EQ. 56)
100
10
10k
100k
1M
10M
SWITCHING FREQUENCY (Hz)
FIGURE 25. R_T vs SWITCHING FREQUENCY
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0.3 _{IL(P-P) = 0}
I_L(P-P) = 0.25 I_O
I_L(P-P) = 0.5 I_O
I_L(P-P) = 0.75 I_O
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (V_O/V_IN)
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 4-PHASE CONVERTER
For a 4-phase design, use Figure 26 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (I_O), and the ratio
of the peak-to-peak inductor current (I_L(P-P)) to I_O. Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated.
The voltage rating of the capacitors should also be at least
1.25x greater than the maximum input voltage. Figures 27
and 28 provide the same input RMS current information for
35
FN6880.1
April 29, 2010