ISL6324A Datasheet, PDF(28/39 Page) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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ISL6324A Datasheet, PDF (28/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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ISL6324A

TABLE 8. BITS [5:0] REGISTER RGS1 and RGS2

(VOLTAGE MARGINING OFFSET) (Continued)

BIT5

VO5

BIT4

VO4

BIT3

VO3

BIT2

VO2

BIT1

VO1

BIT0

VO0

VOFFSET

(mV)

750

775

The bits for Register RGS3 control some of the functionality

of the ISL6324A for Power Savings Mode. Bits 0 and 1

control the number of phases that the ISL6324A will drop to

when in Power Savings Mode. Bits 2 and 3 control the

number of PWM cycles between adding of phases when

exiting Power Savings Mode. Bits 4 and 5 control the

number of PWM cycles between dropping of phases when

entering Power Savings Mode. Bit 6 will disable/enable the

Core DAC offset when in Power Savings Mode. Bit 7 is

reserved. See Table 9 for a complete description of register

RGS3 bits and their functionality.

TABLE 9. BITS [7:0] REGISTER RGS3

Bit 7

Reserved

Bit 6

Core DAC Offset

ENABLED

DISABLED

Bits [5:4] Number of PWM Cycles Between Dropping Phases

1 PWM Cycle (default)

2 PWM Cycles

4 PWM Cycles

0 PWM Cycles (All Phases Drop at Once)

Bits [3:2] Number of PWM Cycles Between Adding Phases

1 PWM Cycle (Default)

2 PWM Cycles

4 PWM Cycles

0 PWM Cycles (All Phases Added at Once)

Bits [1:0] Number of Phases Active in Power Savings Mode

1 Phase

2 Phases (Default)

3 Phases

General Design Guide

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multi-phase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced in the

following sections. In addition to this guide, Intersil provides

complete reference designs that include schematics, bills of

materials, and example board layouts for all common

microprocessor applications.

Power Stages

The first step in designing a multi-phase converter is to

determine the number of phases. This determination depends

heavily on the cost analysis which in turn depends on system

constraints that differ from one design to the next. Principally,

the designer will be concerned with whether components can

be mounted on both sides of the circuit board, whether

through-hole components are permitted, the total board space

available for power-supply circuitry, and the maximum amount

of load current. Generally speaking, the most economical

solutions are those in which each phase handles between

25A and 30A. All surface-mount designs will tend toward the

lower end of this current range. If through-hole MOSFETs and

inductors can be used, higher per-phase currents are

possible. In cases where board space is the limiting

constraint, current can be pushed as high as 40A per phase,

but these designs require heat sinks and forced air to cool the

MOSFETs, inductors and heat dissipating surfaces.

MOSFETS

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

LOWER MOSFET POWER CALCULATION

The calculation for power loss in the lower MOSFET is

simple, since virtually all of the loss in the lower MOSFET is

due to current conducted through the channel resistance

(rDS(ON)). In Equation 19, IM is the maximum continuous

output current, IP-P is the peak-to-peak inductor current (see

Equation 20), and d is the duty cycle (VOUT/VIN).

PLOW, 1 = rDS(ON) â

I--M---ââ

Nâ

(

)

I--L----(--P-----â----P---)--2-----â---(--1-----â-----d----)

(EQ. 19)

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

diode forward voltage at IM, VD(ON), the switching

frequency, fS, and the length of dead times, td1 and td2, at

the beginning and the end of the lower-MOSFET conduction

interval respectively.

PLOW, 2

VD(ON) â fS â

I--M----

I--P-----2-â----P---â ââ

td1

I--M----

I--P-----2-+-----P--â âââ

td2

(EQ. 20)

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of PLOW,1 and PLOW,2.

UPPER MOSFET POWER CALCULATION

In addition to rDS(ON) losses, a large portion of the upper

MOSFET losses are due to currents conducted across the

input voltage (VIN) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent on

switching frequency, the power calculation is more complex.

FN6880.1

April 29, 2010

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