ISL6324A Datasheet, PDF (14/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
current through R_ISEN which is proportional to the inductor
current. This current, I_SEN, is continuously sensed and is
then used by the controller for load-line regulation, channel-
current balancing, and overcurrent detection and limiting.
Equation 9 shows that the proportion between the channel
current, I_L, and the sensed current, I_SEN, is driven by the
value of the effective sense resistance, R_ISEN, and the DCR
of the inductor.
I_SEN
=
I_L ⋅
---^D----^C-----^R-----
R_ISEN
(EQ. 9)
The effective internal R_ISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal R_ISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, R_SET, from the RSET pin to the
VCC pin programs the effective internal R_ISEN resistance
according to Equation 10.
R_ISEN
=
----³-----
400
⋅
R_SET
(EQ. 10)
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R_SET resistor
will program all the effective internal R_ISEN resistors to the
same value.
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I_n,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I_AVG, provides a measure of the total load
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I_AVG, is compared with the Channel 1
sample, I₁, to create an error signal I_ER.
The filtered error signal modifies the pulse width
commanded by V_COMP to correct any unbalance and force
I_ER toward zero. The same method for error signal
correction is applied to each active channel.
.
V_COMP
+
-
FILTER f(s)
MODULATOR
RAMP
WAVEFORM
PWM1
+
-
I_ER
I_AVG
-
÷N
+
I₄
Σ
I₃
I₂
TO GATE
CONTROL
LOGIC
I₁
NOTE: Channel 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
VID Interface
The ISL6324A supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL
pin is used to command the ISL6324A into either the PVI
mode or the SVI mode. Whenever the EN pin is held LOW,
both the multi-phase Core and single-phase North Bridge
Regulators are disabled and the ISL6324A is continuously
sampling voltage on the VID1/SEL pin. When the EN pin is
toggled HIGH, the status of the VID1/SEL pin will latch the
ISL6324A into either PVI or SVI mode. This latching occurs
on the rising edge of the EN signal.If the VID1/SEL pin is
held LOW during the latch, the ISL6324A will be placed into
SVI mode. If the VID1/SEL pin is held HIGH during the latch,
the ISL6324A will be placed into PVI mode. For the
ISL6324A to properly enter into either mode, the level on the
VID1/SEL pin must be stable no less that 1µs prior to the EN
signal transitioning from low to high.
6-bit Parallel VID Interface (PVI)
With the ISL6324A in PVI mode, the single-phase North
Bridge regulator is disabled. Only the multi-phase controller
is active in PVI mode to support uniplane VDD only
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
VID5
0
0
0
0
0
0
0
0
TABLE 1. 6-BIT PARALLEL VID CODES
VID4 VID3 VID2 VID1 VID0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
VREF
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
14
FN6880.1
April 29, 2010