ISL6324A Datasheet, PDF (17/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
to start-up VID values. Details of the SVI Bus protocol are
If the PWROK input is de-asserted, then the controller steps
provided in the AMD Design Guide for Voltage Regulator
both VDD and VDDNB planes back to the stored
Controllers Accepting Serial VID Codes specification.
Pre-PWROK metal VID level in the holding register from
Once the set VID command is received, the ISL6324A
decodes the information to determine which plane and the
VID target required. See Table 4. The internal DAC circuitry
initial soft-start. No attempt is made to read the SVC and
SVD inputs during this time. If PWROK is reasserted, then
the on-board SVI interface waits for a set VID command.
steps the required output plane voltage to the new VID level.
If VDDPWRGD deasserts during normal operation, both
During this time one or both of the planes could be targeted.
voltage planes are powered down in a controlled fashion.
In the event the core voltage plane, VDD, is commanded to
The internal DAC circuitry stair steps both outputs down to
power off by serial VID commands, the VDDPWRGD signal
near zero.
remains asserted. The Northbridge voltage plane must
remain active during this time.
TABLE 4. SERIAL VID CODES
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
SVID[6:0]
VOLTAGE (V)
000_0000b
1.5500
010_0000b
1.1500
100_0000b
0.7500
110_0000b
0.3500*
000_0001b
1.5375
010_0001b
1.1375
100_0001b
0.7375
110_0001b
0.3375*
000_0010b
1.5250
010_0010b
1.1250
100_0010b
0.7250
110_0010b
0.3250*
000_0011b
1.5125
010_0011b
1.1125
100_0011b
0.7125
110_0011b
0.3125*
000_0100b
1.5000
010_0100b
1.1000
100_0100b
0.7000
110_0100b
0.3000*
000_0101b
1.4875
010_0101b
1.0875
100_0101b
0.6875
110_0101b
0.2875*
000_0110b
1.4750
010_0110b
1.0750
100_0110b
0.6750
110_0110b
0.2750*
000_0111b
1.4625
010_0111b
1.0625
100_0111b
0.6625
110_0111b
0.2625*
000_1000b
1.4500
010_1000b
1.0500
100_1000b
0.6500
110_1000b
0.2500*
000_1001b
1.4375
010_1001b
1.0375
100_1001b
0.6375
110_1001b
0.2375*
000_1010b
1.4250
010_1010b
1.0250
100_1010b
0.6250
110_1010b
0.2250*
000_1011b
1.4125
010_1011b
1.0125
100_1011b
0.6125
110_1011b
0.2125*
000_1100b
1.4000
010_1100b
1.0000
100_1100b
0.6000
110_1100b
0.2000*
000_1101b
1.3875
010_1101b
0.9875
100_1101b
0.5875
110_1101b
0.1875*
000_1110b
1.3750
010_1110b
0.9750
100_1110b
0.5750
110_1110b
0.1750*
000_1111b
1.3625
010_1111b
0.9625
100_1111b
0.5625
110_1111b
0.1625*
001_0000b
1.3500
011_0000b
0.9500
101_0000b
0.5500
111_0000b
0.1500*
001_0001b
1.3375
011_0001b
0.9375
101_0001b
0.5375
111_0001b
0.1375*
001_0010b
1.3250
011_0010b
0.9250
101_0010b
0.5250
111_0010b
0.1250*
001_0011b
1.3125
011_0011b
0.9125
101_0011b
0.5125
111_0011b
0.1125*
001_0100b
1.3000
011_0100b
0.9000
101_0100b
0.5000
111_0100b
0.1000*
001_0101b
1.2875
011_0101b
0.8875
101_0101b
0.4875*
111_0101b
0.0875*
001_0110b
1.2750
011_0110b
0.8750
101_0110b
0.4750*
111_0110b
0.0750*
001_0111b
1.2625
011_0111b
0.8625
101_0111b
0.4625*
111_0111b
0.0625*
001_1000b
1.2500
011_1000b
0.8500
101_1000b
0.4500*
111_1000b
0.0500*
001_1001b
1.2375
011_1001b
0.8375
101_1001b
0.4375*
111_1001b
0.0375*
001_1010b
1.2250
011_1010b
0.8250
101_1010b
0.4250*
111_1010b
0.0250*
001_1011b
1.2125
011_1011b
0.8125
101_1011b
0.4125*
111_1011b
0.0125*
001_1100b
1.2000
011_1100b
0.8000
101_1100b
0.4000*
111_1100b
OFF
001_1101b
1.1875
011_1101b
0.7875
101_1101b
0.3875*
111_1101b
OFF
001_1110b
1.1750
011_1110b
0.7750
101_1110b
0.3750*
111_1110b
OFF
001_1111b
1.1625
011_1111b
0.7625
101_1111b
0.3625*
111_1111b
OFF
NOTE: * Indicates a VID not required for AMD Family 10h processors.
17
FN6880.1
April 29, 2010