ISL6324A Datasheet, PDF (18/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
POWER SAVINGS MODE: PSI_L
Bit 7 of the Serial VID code transmitted as part of the 8-bit
data phase over the SVI bus is allocated for the PSI_L. If
Bit 7 is 0, then the processor is at an optimal load for the
regulator to enter power savings mode. If Bit 7 is 1, then the
regulator should not be in power savings mode.
With the ISL6324A, Power Savings mode is realized through
phase shedding. Once a Serial VID command with Bit 7 set
to 0 is received, the ISL6324A will shed phases in a
sequential manner. The default number of phases that the
ISL6324A will run on in Power Savings Mode is two. This
number is programmable through the I²C interface and can
be set to three phases or to one phase (See “I2C Bus
Interface” on page 23). Phases are shed decrementally,
starting with Channel 4. When a phase is shed, that phase
will not go into a tri-state mode until that phase would have
had its PWM go HIGH.
After a phase is shed, the ISL6324A will wait, by default,
1 full PWM cycle before shedding the next phase. This delay
can be changed to 0, 2 or 4 PWM cycle delays through the
I²C interface (See “I2C Bus Interface” on page 23). It should
be noted that with a 0 cycle delay, all phases that are to be
shed will be turned off at the same time. While the option to
shed all phases at once is available, it is not recommended
as the Core voltage could be subjected to large output
deviations during the transition.
When leaving Power Savings Mode, through the reception of
a Serial VID command with Bit 7 set to 1, the ISL6324A will
sequentially turn on phases starting with the lowest
numbered phase that has been shed. When a phase is
being reactivated, it will not leave a tri-state until the PWM of
that phase goes HIGH.
After a phase is reactivated, the ISL6324A will wait, by
default, 1 full PWM cycle before reactivating the next phase.
This delay can be changed to 0, 2 or 4 PWM cycle delays
through the I²C interface (See “I2C Bus Interface” on
page 23). It should be noted that with a 0 cycle delay, all
phases that have been shed will be turned on at the same
time. While the option to reactivate all phases at once is
available, it is not recommended as the Core voltage could
be subjected to large output deviations during the transition.
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining
Bit 7 at 0, the ISL632A will first exit the Power Savings Mode
state as previously described. The output voltage will then
be stepped up or down to the appropriate VID level. Finally,
the ISL6324A will then re-enter Power Savings Mode.
If the Core regulator has had an offset voltage added to the
DAC through the I²C interface, this offset will, by default,
remain while in Power Savings Mode. Through the I²C
interface, the offset can be disabled while in Power Savings
Mode (See “I2C Bus Interface” on page 23).
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6324A to include the
combined tolerances of each of these elements.
The output of the error amplifier, V_COMP, is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 11. The internal and external circuitry
that controls voltage regulation is illustrated in Figure 8.
V_OUT = V_REF – V_DROOP
(EQ. 11)
The ISL6324A incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
EXTERNAL CIRCUIT
FS
R_FS
COMP
ISL6324A INTERNAL CIRCUIT
DROOP
CONTROL
TO
OSCILLATOR
C_C
R_C
FB
R_FB
+
V_DROOP
-
+
V_OUT
-
VSEN
RGND
I_AVG
-
V_COMP
+ _ERROR
AMPLIFIER
∑⁺
+
VID
DAC
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
18
FN6880.1
April 29, 2010