ISL6324A Datasheet, PDF(22/39 Page) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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ISL6324A Datasheet, PDF (22/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

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ISL6324A

12.5ÂµA

INB

OCP

NB ONLY

OCL

17.5ÂµA

REPEAT FOR EACH

CORE CHANNEL

OCP

12.5ÂµA

IAVG

CORE ONLY

SOFT-START, FAULT

AND CONTROL LOGIC

DUPLICATED FOR

NB AND CORE 1.8V

OVP

DAC + 250mV

VSEN

DAC - 300mV

VDDPWRGD

ISL6324A INTERNAL CIRCUITRY

FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY

Fault Monitoring and Protection

The ISL6324A actively monitors both CORE and NB output

voltages and currents to detect fault conditions. Fault

monitors trigger protective measures to prevent damage to

either load. One common power-good indicator is provided

for linking to external system monitors. The schematic in

Figure 13 outlines the interaction between the fault monitors

and the power good signal.

Power-Good Signal

The power good pin (VDDPWRGD) is an open-drain logic

output that signals whether or not the ISL6324A is regulating

both NB and CORE output voltages within the proper levels,

and whether any fault conditions exist. This pin should be

tied to a +5V source through a resistor.

During shutdown and soft-start, VDDPWRGD pulls low and

releases high after a successful soft-start and both output

voltages are operating between the undervoltage and

overvoltage limits. VDDPWRGD transitions low when an

undervoltage, overvoltage, or overcurrent condition is

detected on either regulator output or when the controller is

disabled by a POR reset or EN. In the event of an

overvoltage or overcurrent condition, the controller latches

off and VDDPWRGD will not return high. Pending a POR

reset of the ISL6324A and successful soft-start, the

VDDPWRGD will return high.

Overvoltage Protection

The ISL6324A constantly monitors the sensed output voltage

on the VSEN pin to detect if an overvoltage event occurs.

When the output voltage rises above the OVP trip level and

exceeds the VDDPWRGD OV limit actions are taken by the

ISL6324A to protect the microprocessor load.

At the inception of an overvoltage event, both on-board

lower gate pins are commanded low as are the active PWM

outputs to the external drivers, the VDDPWRGD signal is

driven low, and the ISL6324A latches off normal PWM

action. This turns on the all of the lower MOSFETs and pulls

the output voltage below a level that might cause damage to

the load. The lower MOSFETs remain driven ON until VDIFF

falls below 400mV. The ISL6324A will continue to protect the

load in this fashion as long as the overvoltage condition

recurs. Once an overvoltage condition ends the ISL6324A

latches off, and must be reset by toggling POR, before a

soft-start can be re-initiated.

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the

ISL6324A is designed to protect either load from any

overvoltage events that may occur. This is accomplished by

LGATE, which turns on the lower MOSFET to control the

output voltage until the overvoltage event ceases or the input

power supply cuts off. For complete protection, the low side

MOSFET should have a gate threshold well below the

maximum voltage rating of the load/microprocessor.

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events.

Undervoltage Detection

The undervoltage threshold is set at VDAC - 300mV typical.

When the output voltage (VSEN-RGND) is below the

undervoltage threshold, VDDPWRGD gets pulled low. No

other action is taken by the controller. VDDPWRGD will

return high if the output voltage rises above VDAC - 250mV

typical.

Open Sense Line Protection

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL6324A is designed to detect this

and shut down the controller. This event is detected by

monitoring small currents that are fed out the VSEN and

RGND pins. In the event of an open sense line fault, the

controller will continue to remain off until the fault goes away,

at which point the controller will re-initiate a soft-start

sequence.

Overcurrent Protection

The ISL6324A takes advantage of the proportionality

between the load current and the average current, IAVG, to

detect an overcurrent condition. See âContinuous Current

FN6880.1

April 29, 2010

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