ISL6324A Datasheet, PDF (16/39 Pages) Intersil Corporation – Monolithic Dual PWM Hybrid Controller Powering AMD SVI Split-Plane and PVI Uniplane Processors

ISL6324A
VCC
SVC
SVD
ENABLE
PWROK
VDD AND VDDNB
VDDPWRGD
VFIXEN
1
2
3
456
7
8
9 10
11
12
METAL_VID
V_SVI
METAL_VID
V_SVI
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
PRE-PWROK METAL VID
Typical motherboard start-up occurs with the VFIXEN input
low. The controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the
POR circuitry is satisfied, the ISL6324A begins decoding the
inputs per Table 2. Once the EN input exceeds the rising
enable threshold, the ISL6324A saves the Pre-PWROK
metal VID value in an on-board holding register and passes
this target to the internal DAC circuitry.
TABLE 2. PRE-PWROK METAL VID CODES
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
The Pre-PWROK metal VID code is decoded and latched on
the rising edge of the enable signal. Once enabled, the
ISL6324A passes the Pre-PWROK metal VID code on to
internal DAC circuitry. The internal DAC circuitry begins to
ramp both the VDD and VDDNB planes to the decoded
Pre-PWROK metal VID output level. The digital soft-start
circuitry actually stair steps the internal reference to the
target gradually over a fix interval. The controlled ramp of
both output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
VDDPWRGD output transitions high indicating both output
planes are within regulation limits.
If the EN input falls below the enable falling threshold, the
ISL6324A ramps the internal reference voltage down to near
zero. The VDDPWRGD de-asserts with the loss of enable.
The VDD and VDDNB planes will linearly decrease to near
zero.
VFIX MODE
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed
external to the controller through jumpers to either GND or
VDDIO. These inputs are not expected to change, but the
ISL6324A is designed to support the potential change of
state of these inputs. If VFIXEN is high, the IC decodes the
SVC and SVD states per Table 3.
Once enabled, the ISL6324A begins to soft-start both VDD
and VDDNB planes to the programmed VFIX level. The
internal soft-start circuitry slowly stair steps the reference up
to the target value and this results in a controlled ramp of the
power planes. Once soft-start has ended and both output
planes are within regulation limits, the VDDPWRGD pin
transitions high. If the EN input falls below the enable falling
threshold, then the controller ramps both VDD and VDDNB
down to near zero.
TABLE 3. VFIXEN VID CODES
SVC
SVD
OUTPUT VOLTAGE (V)
0
0
1.4
0
1
1.2
1
0
1.0
1
1
0.8
SVI MODE
Once the controller has successfully soft-started and
VDDPWRGD transitions high, the Northbridge SVI interface
can assert PWROK to signal the ISL6324A to prepare for
SVI commands. The controller actively monitors the SVI
interface for set VID commands to move the plane voltages
16
FN6880.1
April 29, 2010