82443BX Datasheet, PDF (97/132 Pages) Intel Corporation – Host Bridge/Controller

Functional Description
Table 4-5. Host Bus Transactions Supported By 82443BX
Transaction
REQA[4:0]#
REQB[4:0]#
Deferred Reply
Reserved
00000
00001
XXXXX
XXXXX
Interrupt Acknowledge 0 1 0 0 0
Special Transactions
Reserved
Reserved
01000
01000
01000
Branch Trace Message 0 1 0 0 1
Reserved
Reserved
Reserved
01001
01001
01001
00000
00001
0001x
001xx
00000
00001
0001x
001xx
I/O Read
10000
0 0 x LEN#
I/O Write
Reserved
Memory Read &
Invalidate
Reserved
Memory Code Read
10001
1100x
00010
00011
00100
0 0 x LEN#
00xxx
0 0 x LEN#
0 0 x LEN#
0 0 x LEN#
Memory Data Read
00110
0 0 x LEN#
Memory Write (no retry) 0 0 1 0 1
Memory Write (can be
retried)
00111
0 0 x LEN#
0 0 x LEN#
82443BX Support
The 82443BX initiates a deferred reply for a
previously deferred transaction.
Reserved
Interrupt acknowledge cycles are forwarded to
the PCI bus.
See separate table in Special Cycles section.
Reserved
Reserved
The 82443BX terminates a branch trace
message without latching data.
Reserved
Reserved
Reserved
I/O read cycles are forwarded to PCI or AGP.
I/O cycles which are in the 82443BX
configuration space are not forwarded to PCI.
I/O write cycles are forwarded to PCI or AGP.
I/O cycles which are in the 82443BX
configuration space are not forwarded to PCI.
Reserved
Host initiated memory read cycles are
forwarded to DRAM or the PCI/1 bus. The
82443BX initiates an MRI cycle for a PCI/1
initiated write cycle to DRAM.
Reserved
Memory code read cycles are forwarded to
DRAM or PCI/1.
Host initiated memory read cycles are
forwarded to DRAM or the PCI/1 bus. The
82443BX initiates a memory read cycle for a
PCI/1 initiated read cycle to DRAM.
This memory write is a writeback cycle and
cannot be retried. The 82443BX forwards the
write to DRAM.
The normal memory write cycle is forwarded
to DRAM or PCI/1.
NOTE:
1. For Memory cycles, REQa[4:3]# = ASZ#. The 82443BX only supports ASZ# = 00 (32 bit address).
2. REQb[4:3]# = DSZ#. For the Pentium^® Pro processor, DSZ# = 00 (64 bit data bus size).
3. LEN# = data transfer length as follows:
LEN# Data length
00
≤ 8 bytes (BE[7:0]# specify granularity)
01
Length = 16 bytes BE[7:0]# all active
10
Length = 32 bytes BE[7:0]# all active
11
Reserved
82443BX Host Bridge Datasheet
4-11