82443BX Datasheet, PDF (122/132 Pages) Intel Corporation – Host Bridge/Controller

Functional Description
4.8.5
4.8.6
SDRAM Power Down Mode
The 82443BX supports a SDRAM power down mode to minimize SDRAM power usage. The
82443BX controls the SDRAM power mode per row, when all banks in a given row are idle, the
associated CKE signal is deasserted. When a powered down row address is requested, the
associated CKE is asserted.
SMRAM
SMRAM ranges
The 82443BX supports the use of main memory as System Management RAM (SMRAM)
enabling the use of System Management Mode. There are two SMRAM options: Compatible
SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM). System Management RAM
(SMRAM) space provides a memory area that is available for the SMI handler's and code and data
storage. This memory resource is normally hidden from the operating system so that the processor
has immediate access to this memory space upon entry to SMM. 82443BX provides three SMRAM
options:
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
• Optional larger write-back cacheable T_SEG area from 128KB to 1MB in size above 1 MB
that is reserved from the highest area in system DRAM memory. The above 1 MB solutions
require changes to compatible SMRAM handlers code to properly execute above 1 MB.
Compatible SMRAM (C_SMRAM)
This is the traditional SMRAM feature supported in Intel AGPsets. When this function is enabled
via C_BASE_SEG[2:0]=010 and G_SMRAME=1 of the SMRAMC register, the 82443BX
reserves 000A0000h through 000BFFFFh (A and B segments) of the main memory for use as non-
cacheable SMRAM.
The SMI handler can set the CLS bit to enable data accesses to aliased memory space, while code
fetches access the SMRAM space.
Extended SMRAM (E_SMRAM)
This feature in the 82443BX extend the SMRAM space up to 1 MB and provide write-back
cacheability.
The TSEG size is 128 KBs, 256 KBs, 512 KBs or 1 MB, as defined by TSEG_SZ[1:0] of the
SMRAMC register.
The CPU can access these memory ranges by one of the following mechanisms:
• The processor can access SMRAM while in the SMM mode. A processor access to while not
in SMM and with while the D_OPN bit is reset will be forwarded to PCI bus and a status bit is
set in the SMRAMC register.
• The processor can access SMRAM while the D_OPN bit is set.
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82443BX Host Bridge Datasheet