82443BX Datasheet, PDF (34/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.3
Host-to-PCI Bridge Registers (Device 0)
Table 3-1 shows the 82443BX configuration space for device #0.
Table 3-1. 82443BX Register Map — Device 0 (Sheet 1 of 2)
Address
Offset
Register
Symbol
00–01h
02–03h
04–05h
06–07h
08
09
0Ah
0Bh
0Ch
0Dh
0Eh
10–13h
14–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
35–4Fh
VID
DID
PCICMD
PCISTS
RID
—
SUBC
BCC
—
MLT
HDR
APBASE
—
SVID
SID
—
CAPPTR
—
Register Name
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification
Reserved
Sub-Class Code
Base Class Code
Reserved
Master Latency Timer
Header Type
Aperture Base Address
Reserved
Subsystem Vendor Identification
Subsystem Identification
Reserved
Capabilities Pointer
Reserved
50–53h NBXCFG
440BX Configuration
54–56h
57h
58h
59–5Fh
60–67h
68h
69–6Eh
6F–70h
71h
72h
73h
74–75h
76–77h
78–79h
7Ah
7B–7Ch
7D–7Fh
—
DRAMC
DRAMT
PAM[6:0]
DRB[7:0]
FDHC
MBSC
—
—
SMRAM
ESMRAMC
RPS
SDRAMC
PGPOL
PMCR
SCRR
—
Reserved
DRAM Control
DRAM Timing
Programmable Attribute Map (7 registers)
DRAM Row Boundary (8 registers)
Fixed DRAM Hole Control
Memory Buffer Strength Control
Reserved
Intel Reserved
System Management RAM Control
Extended System Management RAM Control.
SDRAM Row Page Size
SDRAM Control Register
Paging Policy Register
Power Management Control Register
Suspend CBR Refresh Rate Register
Reserved
Default Value
Access
8086h
7190h/7192h
0006h
0210h/0200h
00/01h/02h
00h
00h
06h
00h
00h
00h
00000008h
00h
00h
00h
00h
A0h/00h
00h
[0000h]:[00S0_00
00_000S_0S00b]
00h
00S0_0000b
03h
00h
01h
00h
0000-0000-0000h
00h
1Fh
02h
38h
0000h
0000h
00h
0000_S0S0b
0038h
00h
RO
RO
R/W
RO, R/WC
RO
—
RO
RO
—
R/W
RO
R/W,RO
—
R/WO
R/WO
—
RO
—
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
3-8
82443BX Host Bridge Datasheet