82443BX Datasheet, PDF (62/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.3.29
ERRCMD—Error Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
90h
80h
Read/Write
8 bits
This 8-bit register controls the 82443BX responses to various system errors. The actual assertion of
SERR# is enabled via the PCI Command register.
Bit
Description
SERR# on AGP Non-Snoopable Access Outside of Graphics Aperture. When enabled and
bit 10 of ERRSTS registers transitions from 0 to 1 (during an AGP access to the address outside
7
of the graphics aperture) then an SERR# assertion event will be generated.
1 = Enable (default).
0 = Disable.
SERR# on Invalid AGP DRAM Access. AGP non-snoopable READ accesses to locations
outside the graphics aperture and outside the main DRAM range (i.e., in 640 KB – 1 MB range or
above top of memory) are invalid. When this bit is set, bit 9 of the ERRSTS will be set and
6
SERR# will be asserted, read accesses are not directed to main memory or the aperture range.
1 = Enable.
0 = Disable reporting of this condition via SERR#.
SERR# on Access to Invalid Graphics Aperture Translation Table Entry. When enabled, the
82443BX sets bit 8 of the ERRSTS and asserts SERR# following a read or write access to an
5
invalid entry in the Graphics Aperture Translation Table residing in main memory.
1 = Enable.
0 = Disable reporting of this condition via SERR#.
SERR# on Receiving Target Abort.
4
1 = Enable. The 82443BX asserts SERR# on receiving a target abort on either the PCI or AGP.
0 = Disable. The 82443BX does not assert SERR# on receipt of a target abort.
SERR# on Detected Thermal Throttling Condition.
3
1 = Enable. The 82443BX asserts SERR# when thermal throttling condition is detected for either
the read or the write function.
0 = The 82443BX does not assert SERR# for thermal throttling.
SERR# Assertion Mode.
2
1 = SERR# is a level mode signal. Systems that connect SERR# to EXTSMI# for error reporting
should set this bit to 1.
0 = SERR# is asserted for 1 PCI clock (normal PCI mode). (default)
SERR# on Receiving Multiple-Bit ECC/Parity Error. When enabled, the 82443BX asserts
SERR# when it detects a multiple-bit error reported by the DRAM controller. For systems not
supporting ECC this bit must be disabled.
1
1 = Enable.
0 = Disable.
Note: Any ECC errors received during initialization should be ignored.
SERR# on Receiving Single-bit ECC Error. When enabled, the 82443BX asserts SERR#
when it detects a single-bit ECC error. For systems not supporting ECC, this bit must be
disabled.
0
1 = Enable.
0 = Disable.
Note: Any ECC errors received during initialization should be ignored.
3-36
82443BX Host Bridge Datasheet