82443BX Datasheet, PDF (21/132 Pages) Intel Corporation – Host Bridge/Controller

Signal Description
2.5
AGP Interface Signals
There are 17 new signals added to the normal PCI group of signals that together constitute the AGP
interface. The sections below describe their operation and use, and are organized in five groups:
• AGP Addressing Signals
• AGP Flow Control Signals
• AGP Status Signals
• AGP Clocking Signals - Strobes
• PCI Signals
Table 2-6. AGP Interface Signals (Sheet 1 of 2)
Name
PIPE#
SBA[7:0]
RBF#
ST[2:0]
Type
I
AGP
I
AGP
I
AGP
O
AGP
Description
AGP Sideband Addressing Signals¹
Pipelined Read: This signal is asserted by the current master to indicate a full width
address is to be queued by the target. The master queues one request each rising
clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are
queued across the AD bus. PIPE# is a sustained tri-state signal from masters
(graphics controller) and is an input to the 82443BX. Note that initial AGP designs
may not use PIPE#.
Sideband Address: This bus provides an additional bus to pass address and
command to the 82443BX from the AGP master. Note that, when sideband
addressing is disabled, these signals are isolated (no external/internal pull-ups are
required).
AGP Flow Control Signals
Read Buffer Full. This signal indicates if the master is ready to accept previously
requested low priority read data. When RBF# is asserted the 82443BX is not allowed
to return low priority read data to the AGP master on the first block. RBF# is only
sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is not required to
implement this signal.
AGP Status Signals
Status Bus: This bus provides information from the arbiter to a AGP Master on what
it may do. ST[2:0] only have meaning to the master when its GGNT# is asserted.
When GGNT# is deasserted these signals have no meaning and must be ignored.
000 Indicates that previously requested low priority read data is being returned to
the master.
001 Indicates that previously requested high priority read data is being returned to
the master.
010 Indicates that the master is to provide low priority write data for a previously
queued write command.
011 Indicates that the master is to provide high priority write data for a previously
queued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the master has been given permission to start a bus transaction.
The master may queue AGP requests by asserting PIPE# or start a PCI
transaction by asserting FRAME#. ST[2:0] are always an output from the
82443BX and an input to the master.
82443BX Host Bridge Datasheet
2-7