82443BX Datasheet, PDF (78/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.4.6
3.4.7
3.4.8
SUBC1—Sub-Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Ah
04h
Read Only
8 bits
This register contains the Sub-Class Code for the 82443BX device #1. This code is 04h indicating a
PCI-to-PCI Bridge device. The register is read only.
Bit
Description
Sub-Class Code (SUBC1). This is an 8-bit value that indicates the category of Bridge into which
7:0
the 82443BX falls.
04h = Host Bridge.
BCC1—Base Class Code Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Bh
06h
Read Only
8 bits
This register contains the Base Class Code of the 82443BX device #1. This code is 06h indicating a
Bridge device. This register is read only.
Bit
Description
Base Class Code (BASCC). This is an 8-bit value that indicates the Base Class Code for the
7:0
82443BX device #1.
06h = Bridge device.
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
0Dh
00h
Read/Write
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
read/write to comply with the normal PCI-to-PCI bridge configuration software.
Bit
Description
7:3 Not applicable but support read/write operations. (Reads return previously written data.)
2:0 Reserved.
3-52
82443BX Host Bridge Datasheet