82443BX Datasheet, PDF (19/132 Pages) Intel Corporation – Host Bridge/Controller

Signal Description
2.3
PCI Interface (Primary)
Table 2-4. Primary PCI Interface Signals (Sheet 1 of 2)
Name
AD[31:0]
DEVSEL#
FRAME#
IRDY#
C/BE[3:0]#
PAR
PLOCK#
TRDY#
Type
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
Description
PCI Address/Data: These signals are connected to the PCI address/data bus.
Address is driven by the 82443BX with FRAME# assertion, data is driven or received
in the following clocks. When the 82443BX acts as a target on the PCI Bus, the
AD[31:0] signals are inputs and contain the address during the first clock of FRAME#
assertion and input data (writes) or output data (reads) on subsequent clocks.
Device Select: Device select, when asserted, indicates that a PCI target device has
decoded its address as the target of the current access. The 82443BX asserts
DEVSEL# based on the DRAM address range or AGP address range being accessed
by a PCI initiator. As an input it indicates whether any device on the bus has been
selected.
Frame: FRAME# is an output when the 82443BX acts as an initiator on the PCI Bus.
FRAME# is asserted by the 82443BX to indicate the beginning and duration of an
access. The 82443BX asserts FRAME# to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is negated, the
transaction is in the final data phase. FRAME# is an input when the 82443BX acts as
a PCI target. As a PCI target, the 82443BX latches the C/BE[3:0]# and the AD[31:0]
signals on the first clock edge on which it samples FRAME# active.
Initiator Ready: IRDY# is an output when 82443BX acts as a PCI initiator and an
input when the 82443BX acts as a PCI target. The assertion of IRDY# indicates the
current PCI Bus initiator's ability to complete the current data phase of the
transaction.
Command/Byte Enable: PCI Bus Command and Byte Enable signals are
multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]#
define the bus command. During the data phase C/BE[3:0]# are used as byte
enables. The byte enables determine which byte lanes carry meaningful data. PCI
Bus command encoding and types are listed below.
C/BE[3:0]# Command Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Reserved (Dual Address Cycle)
Memory Read Line
Memory Write and Invalidate
Parity: PAR is driven by the 82443BX when it acts as a PCI initiator during address
and data phases for a write cycle, and during the address phase for a read cycle. PAR
is driven by the 82443BX when it acts as a PCI target during each data phase of a
PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.
Lock: PLOCK# indicates an exclusive bus operation and may require multiple
transactions to complete. When PLOCK# is asserted, non-exclusive transactions may
proceed. The 82443BX supports lock for CPU initiated cycles only. PCI initiated
locked cycles are not supported.
Target Ready: TRDY# is an input when the 82443BX acts as a PCI initiator and an
output when the 82443BX acts as a PCI target. The assertion of TRDY# indicates the
target agent's ability to complete the current data phase of the transaction.
82443BX Host Bridge Datasheet
2-5