82443BX Datasheet, PDF (112/132 Pages) Intel Corporation – Host Bridge/Controller

Functional Description
4.6.1.4 ECC Generation and Error Detection/Correction and Reporting
The 82443BX ECC logic implements the ECC code which is compatible with the algorithm used
for the Pentium Pro processor data bus ECC protection. The code is described in the Pentium Pro
processor bus specification.
ECC Generation
When enabled, the DRAM ECC mechanism allows automatic generation of an 8-bit protection
code for the 64-bit (QWord) of data during DRAM write operations. If the originally requested
write operation transfers single or multiple QWords, then the ECC-protected DRAM writes are
completed with no overhead. That is, ECC code is calculated and written along with the data. If the
originally requested write operation transfers less than 64bits of data (less than a QWord), then the
82443BX performs a READ-MERGE-WRITE operation.
ECC Checking and Correction
When enabled, the ECC mechanism allows a detection of single-bit and multiple-bit errors and
recovery of single-bit errors. During DRAM read operations, a full QWord of data (8 bytes) is
always transferred from DRAM to the 82443BX regardless of the size of the originally requested
data. Both 64-bit data and 8-bit ECC code are transferred simultaneously from DRAM to the
82443BX. The ECC checking logic in the 82443BX generates a new ECC code for the received
64-bit data and compares it with received ECC code. If a single-bit error is detected the ECC logic
generates a new “recovered” 64-bit QWord with a pattern which corresponds to the originally
received 8-bit ECC protection code. The corrected data is returned to the requester (the CPU, PCI
master or AGP master). Additionally, the 82443BX ensures that the data is corrected in main
memory so that accumulation of errors is prevented. Another error within the same QWord would
result in a double-bit error which is unrecoverable. This is known as hardware scrubbing since it
requires no software intervention to correct the data in memory.
ECC Error Reporting
For single-bit error indication, the SEF flag is set by the 82443BX in the ERRSTS (Error Status)
register, along with the row number associated with the first single-bit error. The row number
where the error occurred is stored in the Single-bit First Row Error (SBFRE) field in the Error
Status Register. Similarly, for multiple bit error indication, the MEF flag is set in the ERRSTS
register along with the row number associated with the first multiple bit error. In the case of a
multi-bit error the row number is stored in the Multi-bit First Row Error (MBFRE) field in the
Error Status register. In both single-bit and multiple-bit error cases, after logging the first error, the
Error Status register is locked until the software writes to the respective flags and clears the SEF
and MEF bits. This error condition can also be optionally reported to the system via the SERR#
mechanism. This functionality is controlled by the ERRCMD (Error Command) register. When bit
1 of the Error Command register is set to 1, an occurrence of a multiple bit error is signaled by the
assertion of SERR#. When bit 0 of the Error Command register is set to 1, an occurrence of a single
bit error is signaled by the assertion of SERR#. Reporting of single bit errors via SERR# is not
critical since these errors are not only corrected as data is delivered to the requester and the error is
automatically corrected in memory. However, system software may monitor the occurrence of
single bit errors to indicate the presence of an unreliable DIMM when single bit errors frequently
occur.
Note: Any ECC errors received during initialization should be ignored.
After a single-bit correctable ECC error has occurred, it is reported either via hardware mechanism
or via software mechanism (periodic polling of the ERRSTS register). After a single bit error has
occurred, the 82443BX then initiates a write to the location where the error occurred with the
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82443BX Host Bridge Datasheet