82443BX Datasheet, PDF (47/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
Table 3-2. Attribute Bit Assignment
Bits [7, 3] Bits [6, 2] Bits [5, 1] Bits [4, 0]
Reserved Reserved
WE
RE
Description
Disabled. DRAM is disabled and all accesses are
x
x
0
0
directed to PCI. The 82443BX does not respond as a
PCI target for any read or write access to this area.
Read Only. Reads are forwarded to DRAM and writes
are forwarded to PCI for termination. This write protects
x
x
0
1
the corresponding memory segment. The 82443BX will
respond as a PCI target for read accesses but not for
any write accesses.
Write Only. Writes are forwarded to DRAM and reads
x
x
1
0
are forwarded to the PCI for termination. The 82443BX
will respond as a PCI target for write accesses but not
for any read accesses.
Read/Write. This is the normal operating mode of main
memory. Both read and write cycles from the host are
x
x
1
1
claimed by the 82443BX and forwarded to DRAM. The
82443BX will respond as a PCI target for both read and
write accesses.
As an example, consider a BIOS that is implemented on the expansion bus. During the
initialization process, the BIOS can be shadowed in main memory to increase the system
performance. When BIOS is shadowed in main memory, it should be copied to the same address
location. To shadow the BIOS, the attributes for that address range should be set to write only. The
BIOS is shadowed by first doing a read of that address. This read is forwarded to the expansion bus.
The host then does a write of the same address, which is directed to main memory. After the BIOS
is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded
to the expansion bus. Table 3-3 shows the PAM registers and the associated attribute bits:
Table 3-3. PAM Registers and Associated Memory Segments
PAM Reg
PAM0[3:0]
PAM0[7:4]
PAM1[3:0]
PAM1[7:4]
PAM2[3:0]
PAM2[7:4]
PAM3[3:0]
PAM3[7:4]
PAM4[3:0]
PAM4[7:4]
PAM5[3:0]
PAM5[7:4]
PAM6[3:0]
PAM6[7:4]
Attribute Bits
Reserved
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
R R WE RE
Memory Segment
0F0000h – 0FFFFFh
0C0000h – 0C3FFFh
0C4000h – 0C7FFFh
0C8000h – 0CBFFFh
0CC000h – 0CFFFFh
0D0000h – 0D3FFFh
0D4000h – 0D7FFFh
0D8000h – 0DBFFFh
0DC000h – 0DFFFFh
0E0000h – 0E3FFFh
0E4000h – 0E7FFFh
0E8000h – 0EBFFFh
0EC000h – 0EFFFFh
Comments
BIOS Area
ISA Add-on BIOS¹
ISA Add-on BIOS¹
ISA Add-on BIOS¹
ISA Add-on BIOS¹
ISA Add-on BIOS
ISA Add-on BIOS
ISA Add-on BIOS
ISA Add-on BIOS
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
Offset
59h
59h
5Ah
5Ah
5Bh
5Bh
5Ch
5Ch
5Dh
5Dh
5Eh
5Eh
5Fh
5Fh
NOTE:
1. The C0000h to CFFFFh segment can be used for SMM space if enabled by the SMRAM register
82443BX Host Bridge Datasheet
3-21