82443BX Datasheet, PDF (61/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.3.28
EAP—Error Address Pointer Register (Device 0)
Address Offset:
Default Value:
Access
Size
80–83h
00000000h
Read Only, Read/Write-Clear
32 Bits
Bit
31:12
11:2
1
0
Description
Error Address Pointer (EAP) (RO). This field is used to store the 4 KB block of main memory
of which an error (single bit or multi-bit error) has occurred. Note that this field represents the
address of the first error occurrence after bits 1:0 have been cleared by software. Once bits 1:0
are set to a value different than 00b, as a result of an error, this bit field is locked and doesn't
change as a result of a new error.
Reserved.
Multiple Bit Error (MBE) (R/WC). This bit indicates that a multi-bit ECC error has occurred,
and the address has been logged in bits 31:12. The EAP register is locked until the CPU
clears this bit by writing a 1. Software uses bits 1:0 to detect whether the logged error address
is for Single or Multi bit error, since both Single and Multiple Error bits of the Error Status
register can be set. Once software completes the error processing, a value of ‘1’ is written to
this bit field to clear the value (back to 0) and unlock the error logging mechanism.
Note: Any ECC errors received during initialization should be ignored.
Single Bit Error (SBE) (R/WC).
1 = Indicates that a single bit ECC error has occurred, and the address has been logged in bits
31:12. The EAP register is locked until the CPU clears this bit by writing a 1.
Note: Any ECC errors received during initialization should be ignored.
82443BX Host Bridge Datasheet
3-35