82443BX Datasheet, PDF (117/132 Pages) Intel Corporation – Host Bridge/Controller

Functional Description
Table 4-14. Low Power Mode
System Suspend State
82443BX
State
Description
POS Exit
PCIRST
External Clk
HCLK PCLK
Powered-On
The 82443BX is fully on and
operating normally.
ON
N/A
Internal clock gating as well as PCI
CLKRUN# may be enabled.
CPU STOP_GRANT /
QUICK_START
(C2)
This is transparent to the 82443BX
as external HCLK and PCLK are
ON ^{unaffected. Host Bus is Idle however.}
N/A
Internal clock gating as well as PCI
CLKRUN# may be enabled.
CPU STOP CLOCK (C3)
HCLK clock is kept low. The
POS 82443BX maintains DRAM refresh
N
(DEEP SLEEP)
using suspend refresh.
Powered On Suspend
(POS, POSCL)
The only running clock is the RTC
clock. The 82443BX maintains
POS DRAM refresh using suspend
N
refresh. When resume, the 82443BX
may or may not generate CPU reset.
Powered On Suspend
(POSCL)
The only running clock is the RTC
clock. The 82443BX maintains
DRAM refresh using suspend
Y
refresh. On resume, PIIX4E
generates PCI reset.
Suspend to RAM
(STR)
CPU and other components (with the
exception of DRAM and PIIX4E
resume logic) are assumed to be
powered OFF.
POS
Y
The 82443BX maintains DRAM
refresh using suspend refresh. All
82443BX logic, with the exception of
resume and refresh are inactive.
Entire system is powered OFF except
Suspend -to-Disk (STD)
or Powered-Off
OFF
for PIIX4E resume and RTC wells.
Upon resume, the 82443BX resets its
N/A
entire state.
HCLK PCLK
Active Active
Active Active
Low
Low or
Active
Low
Low
Low
Low
Low
Low
X
X
82443BX Host Bridge Datasheet
4-31