82443BX Datasheet, PDF (13/132 Pages) Intel Corporation – Host Bridge/Controller

Architectural Overview
DRAM Interface
The 82443BX integrates a DRAM controller that supports a 64-bit main memory interface. The
DRAM controller supports the following features:
• DRAM type: Extended Data Out (EDO) (mobile only) or Synchronous (SDRAM) DRAM
controller optimized for dual/quad-bank SDRAM organization on a row by row basis
• Memory Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory rows
• Addressing Type: Symmetrical and Asymmetrical addressing
• Memory Modules supported: Single and double density 3.3V DIMMs
• DRAM device technology: 16 Mbit and 64 Mbit
• DRAM Speeds: 60 ns for EDO and 100/66 MHz for synchronous memory (SDRAM).
The Intel^® 440BX AGPset also provides DIMM plug-and-play support via Serial Presence Detect
(SPD) mechanism using the SMBus interface. The 82443BX provides optional data integrity
features including ECC in the memory array. During reads from DRAM, the 82443BX provides
error checking and correction of the data. The 82443BX supports multiple-bit error detection and
single-bit error correction when ECC mode is enabled and single/multi-bit error detection when
correction is disabled. During writes to the DRAM, the 82443BX generates ECC for the data on a
QWord basis. Partial QWord writes require a read-modify-write cycle when ECC is enabled.
AGP Interface
The 82443BX AGP implementation is compatible with the following:
• The Accelerated Graphics Port Specification, Rev 1.0
• Accelerated Graphics Port Memory Performance Specification, Rev 1.0 (4/12/96)
The 82443BX supports only a synchronous AGP interface coupling to the 82443BX core
frequency. The AGP interface can reach a theoretical ~500 MByte/sec transfer rate (i.e., using
133 MHz AGP compliant devices).
PCI Interface
The 82443BX PCI interface is 3.3V (5V tolerant), 33 MHz Rev. 2.1 compliant and supports up to
five external PCI bus masters in addition to the I/O bridge (PIIX4/PIIX4E). The PCI-to-DRAM
interface can reach over 100 MByte/sec transfer rate for streaming reads and over 120 MBytes/sec
for streaming writes.
System Clocking
The 82443BX operates the host interface at 66 or 100 MHz, the SDRAM/core at 66 or 100 MHz,
PCI at 33 MHz and AGP at 66/133 MHz.
I/O APIC
I/O APIC is used to support dual processors as well as enhanced interrupt processing in the single
processor environment. The 82443BX supports an external status output signal that can be used to
control synchronization of interrupts in configurations that use PIIX4E with stand-alone I/O APIC
component.
82443BX Host Bridge Datasheet
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