82443BX Datasheet, PDF (20/132 Pages) Intel Corporation – Host Bridge/Controller

Signal Description
Table 2-4. Primary PCI Interface Signals (Sheet 2 of 2)
Name
Type
Description
SERR#
STOP#
System Error: The 82443BX asserts this signal to indicate an error condition. The
SERR# assertion by the 82443BX is enabled globally via SERRE bit of the PCICMD
register. SERR# is asserted under the following conditions:
In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable)
ECC errors or multiple bit (non-correctable) ECC errors if SERR# signaling is enabled
via the ERRCMD control register. Any ECC errors received during initialization should
be ignored.
• The 82443BX asserts SERR# for one clock when it detects a target abort during
82443BX initiated PCI cycle.
• The 82443BX can also assert SERR# when a PCI parity error occurs during the
I/O
address or data phase.
PCI
• The 82443BX can assert SERR# when it detects a PCI address or data parity
error on AGP.
• The 82443BX can assert SERR# upon detection of access to an invalid entry in
the Graphics Aperture Translation Table.
• The 82443BX can assert SERR# upon detecting an invalid AGP master access
outside of AGP aperture and outside of main DRAM range (i.e. in the 640k - 1M
range or above TOM).
• The 82443BX can assert SERR# upon detecting an invalid AGP master access
outside of AGP aperture.
• The 82443BX asserts SERR# for one clock when it detects a target abort during
82443BX initiated AGP cycle.
I/O ^{Stop: STOP# is an input when the 82443BX acts as a PCI initiator and an output}
when the 82443BX acts as a PCI target. STOP# is used for disconnect, retry, and
PCI _{abort sequences on the PCI Bus.}
NOTE:
1. All PCI interface signals conform to the PCI Rev 2.1 specification.
2.4
Primary PCI Sideband Interface
Table 2-5. Primary PCI Sideband Interface Signals
Name
Type
Description
PHOLD#
PHLDA#
WSC#
PREQ[4:0]#
PGNT[4:0]#
I
PCI
O
PCI
O
CMOS
I
PCI
O
PCI
PCI Hold: This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus
ownership. The 82443BX will flush and disable the CPU-to-PCI write buffers before
granting the PIIX4E the PCI bus via PHLDA#. This prevents bus deadlock between
PCI and ISA.
PCI Hold Acknowledge: This signal is driven by the 82443BX to grant PCI bus
ownership to the PIIX4E after CPU-PCI post buffers have been flushed and disabled.
Write Snoop Complete. This signal is asserted active to indicate that all that the
snoop activity on the CPU bus on the behalf of the last PCI-DRAM write transaction is
complete and that is safe to send the APIC interrupt message.
PCI Bus Request: PREQ[4:0]# are the PCI bus request signals used as inputs by the
internal PCI arbiter.
PCI Grant: PGNT[4:0]# are the PCI bus grant output signals generated by the internal
PCI arbiter.
2-6
82443BX Host Bridge Datasheet