82443BX Datasheet, PDF (66/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.3.34
AGPCTRL—AGP Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
B0–B3h
00000000h
Read/Write
32 bits
This register provides for additional control of the AGP interface.
Bit
31:16
15
14
13
12:8
7
6:0
Description
Reserved.
Snoopable Writes In Order With AGP Reads Disable (AGPDCD). When set to 0 (default), the
82443BX maintains ordering between snoopable write cycles and AGP reads. When set to 1, the
82443BX handles the AGP reads and snoopable writes as independent streams.
AGPDCD AGPRSE
(Bit 15)
(Bit 13)
Description
0
0
DWB is visible to AGP reads. DWB flushes only when address hit.
0
1
Illegal.
1
0
Illegal
1
1
DWB flushes when write to AGP occurs
Reserved
Graphics Aperture Write-AGP Read Synchronization Enable (AGPRSE). When this bit is set
the 82443BX will ensure that all writes posted in the Global Write Buffer to the Graphics Aperture
are retired to DRAM before the 82443BX will initiate any CPU-to-AGP cycle. This can be used to
ensure synchronization between the CPU and AGP master. The AGPDCD bit description defines
the interaction between the AGPRSE bit and the AGPDCD bit.
1 = Enable
0 = Disable (Default)
Reserved
GTLB Enable (and GTLB Flush Control).
1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer.
0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry.
Reserved.
3-40
82443BX Host Bridge Datasheet