82443BX Datasheet, PDF (22/132 Pages) Intel Corporation – Host Bridge/Controller

Signal Description
Table 2-6. AGP Interface Signals (Sheet 2 of 2)
Name
Type
Description
ADSTB_A
ADSTB_B
SBSTB
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
GGNT#
GAD[31:0]
GC/BE[3:0]#
GPAR
I/O
AGP
I/O
AGP
I
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
I
AGP
O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
AGP Clocking Signals - Strobes
AD Bus Strobe A: This signal provides timing for double clocked data on the AD bus.
The agent that is providing data drives this signal. This signal requires an 8.2K ohm
external pull-up resistor.
AD Bus Strobe B: This signal is an additional copy of the AD_STBA signal. This
signal requires an 8.2K ohm external pull-up resistor.
Sideband Strobe: THis signal provides timing for a side-band bus. This signal
requires an 8.2K ohm external pull-up resistor.
AGP FRAME# Protocol SIgnals (similar to PCI)²
Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains deasserted
by its own pull up resistor.
Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP compliant
master is ready to provide all write data for the current transaction. Once IRDY# is
asserted for a write operation, the master is not allowed to insert wait states. The
assertion of IRDY# for reads indicates that the master is ready to transfer to a
subsequent block (32 bytes) of read data. The master is never allowed to insert wait
states during the initial data transfer (32 bytes) of a read transaction. However, it may
insert wait states after each 32 byte block is transferred.
(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)
Graphics Target Ready: New meaning. GTRDY# indicates the AGP compliant
target is ready to provide read data for the entire transaction (when the transfer size is
less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block
(32 bytes) of data when the transfer size is greater than 32 bytes. The target is
allowed to insert wait states after each block (32 bytes) is transferred on both read
and write transactions.
Graphics Stop: Same as PCI. Not used by AGP.
Graphics Device Select: Same as PCI. Not used by AGP.
Graphics Request: Same as PCI. (Used to request access to the bus to initiate a
PCI or AGP request.)
Graphics Grant: Same meaning as PCI but additional information is provided on
ST[2:0]. The additional information indicates that the selected master is the recipient
of previously requested read data (high or normal priority), it is to provide write data
(high or normal priority), for a previously queued write command or has been given
permission to start a bus transaction (AGP or PCI).
Graphics Address/Data: Same as PCI.
Graphics Command/Byte Enables: Slightly different meaning. Provides command
information (different commands than PCI) when requests are being queued when
using PIPE#. Provide valid byte information during AGP write transactions and are
not used during the return of read data.
Graphics Parity: Same as PCI. Not used on AGP transactions, but used during PCI
transactions as defined by the PCI specification.
NOTE:
1. AGP Sideband Addressing Signals. The above table contains two mechanisms to queue requests by
the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue
addresses the master is not allowed to queue addresses using the SBA bus. For example, during
configuration time, if the master indicates that it can use either mechanism, the configuration software will
indicate which mechanism the master will use. Once this choice has been made, the master will continue to
use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This
change of modes is not a dynamic mechanism but rather a static decision when the device is first being
configured after reset.
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82443BX Host Bridge Datasheet