82443BX Datasheet, PDF (58/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.3.25
PGPOL—Paging Policy Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
78–79h
0000h
Read/Write
16 bits
Bit
Description
Banks per Row (BPR). Each bit in this field corresponds to one row of the memory array. Bit 15
corresponds to row 7 while bit 8 corresponds to row 0. These bits are defined only for SDRAM
systems and define whether the corresponding row has a two bank implementation or a four
bank implementation. Those with two banks (bit=0) can have up to two pages open at any given
15:8
time. Those with four banks (bit=1) can have up to four pages open at any time. Note that the
bits referencing empty rows are ‘don’t care’.
0 = 2 banks
1 = 4 banks
7:5
Reserved.
4
Intel Reserved.
DRAM Idle Timer (DIT). This field determines the number of clocks that the DRAM controller
will remain in the idle state before precharging all pages. This field is used for both EDO and
SDRAM memory systems.
0000 = 0 clocks
0001 = 2 clocks
0010 = 4 clocks
3:0
0011 = 8 clocks
0100 = 10 clocks
0101 = 12 clocks
0110 = 16 clocks
0111 = 32 clocks
1XXX = Infinite (pages are not closed for idle condition).
3-32
82443BX Host Bridge Datasheet