82443BX Datasheet, PDF (44/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
Bit
Description
ECC Diagnostic Mode Enable (EDME) (R/W).
1 = Enable. When this bit is set to 1, the 82443BX will enter ECC Diagnostic test mode and the
6
82443BX forces the MECC[7:0] lines to 00h for all writes to memory. During reads, the read
MECC[7:0] lines are compared against internally generated ECC. Recognized errors are
indicated via the ERRSTS register as in normal ECC operation.
0 = Normal operation mode (default).
MDA Present (MDAP).
This bit is used to indicate the presence of a secondary monochrome adapter on the PCI bus,
while the primary graphics controller is on the AGP bus. This bit works in conjunction with the
VGA_EN bit (Register 3E, bit 3 of device 1) as follows:
VGA_EN MDAP
Description
0
X
All VGA cycles are sent to PCI. PCI master cycles to the VGA range
are not claimed by the 82443BX.
5
1
0
All VGA cycles are sent to AGP. PCI master writes to VGA range are
claimed by the 82443BX and forwarded to the AGP bus.
1
1
All VGA cycles are sent to AGP, except for cycles in the MDA range
(or the aliased ranges defined below). PCI master writes in the VGA
range (outside of the MDA range) are claimed by the 82443BX and
forwarded to AGP. PCI and AGP master read/writes to the MDA range
are ignored by the 82443BX.
The MDA ranges are a subset of the VGA ranges as follows:
Memory: 0B0000h–0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh
4
Reserved.
USWC Write Post During I/O Bridge Access Enable (UWPIO) (R/W).
3
1 = Enable. Host USWC writes to PCI memory are posted.
0 = Disable. Posting of USWC is not allowed.
In-Order Queue Depth (IOQD) (RO). This bit reflects the value sampled on A7# on the
deassertion of the CPURST#. It indicates the depth of the Pentium^® Pro processor bus in-order
queue (i.e., level of Pentium Pro processor bus pipelining).
1 = In-order queue = maximum. If A7# is sampled “1” (i.e,. undriven on the Pentium Pro
processor bus), the depth of the Pentium Pro processor bus in-order queue is configured to
the maximum allowed by the Pentium Pro processor protocol (i.e., 8). However, the actual
2
maximum supported by the 82443BX is 4, and it is controlled by the 82443BX’s Pentium Pro
processor interface logic using the BNR# signaling mechanism.
0 = A7# is sampled asserted (i.e., “0”). The depth of the Pentium Pro processor bus in-order
queue is set to 1 (i.e., no pipelining support on the Pentium Pro processor bus).
NOTE: During reset, A7# can be driven either by the 82443BX or by an external source as defined
by the strapping option on the MAB11# pin.
1:0 Reserved.
3-18
82443BX Host Bridge Datasheet