82443BX Datasheet, PDF (55/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.3.22
ESMRAMC—Extended System Management RAM Control
Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
73h
38h
Read/Write
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 Mbyte.
Bit
Description
H_SMRAM_EN (H_SMRAME). Controls the SMM memory space location (i.e above 1 Mbyte or
below 1 Mbyte).
1 = When G_SMRAME is 1 and H SMRAME is set to 1, the High SMRAM memory space is
enabled, the Compatible SMRAM memory is disabled, and accesses in the 0A0000h to
7
0FFFFFh range are forwarded to PCI, while SMRAM accesses from 100A0000h to
100FFFFFh are remapped to DRAM address A0000h to FFFFFh
0 = When G SMRAME is set to a 1 and H SMRAM EN is set to 0, then the Compatible SMRAM
space is enabled.
Once D_LCK is set, this bit becomes read only.
E_SMRAM_ERR (E_SMERR).
6
1 = This bit is set when CPU accesses the defined memory ranges in Extended SMRAM (High
Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0.
0 = It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it.
5
SMRAM_Cache (SM_CACHE). This bit is forced to ‘1’ by 82443BX.
4
SMRAM_L1_EN (SM_L1). This bit is forced to ‘1’ by 82443BX.
3
SMRAM_L2_EN (SM_L2). This bit is forced to ‘1’ by 82443BX.
TSEG_SZ[1:0] (T_SZ). Selects the size of the TSEG memory block, if enabled. This memory is
taken from the top of DRAM space (i.e., TOM - TSEG_SZ), which is no longer claimed by the
memory controller (all accesses to this space are sent to the PCI bus if TSEG_EN is set). The
physical address for the extended SMRAM memory appears is from (256M + TOM - TSEG_SZ) to
(256M + TOM). This address is remapped to DRAM address (TOM - TSEG_SZ) to TOM. This field
decodes as follows:
2:1
00 = (TOM–128KB) to TOM
01 = (TOM–256KB) to TOM
10 = (TOM–512KB) to TOM
11 = (TOM–1MB) to TOM
Once D_LCK is set, this bit becomes read only.
TSEG_EN (T_EN). Enabling of SMRAM memory (TSEG, 128 KB, 256 KB, 512 KB or 1 MB of
0
additional SMRAM memory) for Extended SMRAM space only. When
G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical
address space. Once D_LCK is set, this bit becomes read only.
82443BX Host Bridge Datasheet
3-29