82443BX Datasheet, PDF (100/132 Pages) Intel Corporation – Host Bridge/Controller

Functional Description
4.3
4.3.1
DRAM Interface
The 82443BX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64-bit
memory data plus 8 ECC) DRAM array. The DRAM types supported are Synchronous (SDRAM)
and Extended Data Out (EDO). The 82443BX does not support mixing of SDRAM and EDO.
When the CPU bus is running at 100 MHz, the 82443BX DRAM interface runs at 100 MHz
(SDRAM only). When the CPU bus is operating at 66 MHz, the 82443BX DRAM interface runs at
66 MHz (SDRAM or EDO). EDO DRAM technology is supported in mobile designs only at 66
MHz. The DRAM controller interface is fully configurable through a set of control registers.
Complete descriptions of these registers are given in the Register Section. A brief overview of the
registers which configure the DRAM interface is provided in this section.
The 82443BX supports industry standard 64/72-bit wide DIMM modules with SDRAM and EDO
DRAM devices. The fourteen multiplexed address lines, MA[13:0], allow the 82443BX to support
1M, 2M, 4M, 8M, and 16M x72/64 DIMMs. Both symmetric and asymmetric addressing is
supported. The 82443BX has sixteen CS# lines, used in pairs enabling the support of up to eight
64/72-bit rows of DRAM. For write operations of less than a QWord in size, the 82443BX will
either perform a byte-wise write (non-ECC protected configuration) or a read-modify-write cycle
by merging the write data on a byte basis with the previously read data (ECC or EC configurations).
The 82443BX targets 60 ns EDO DRAMs and SDRAM with CL2 and CL3 and supports both
single and double-sided DIMMs. When using EDO DRAM, up to 6 rows of memory are supported.
The 82443BX provides refresh functionality with programmable rate (normal DRAM rate is 1
refresh/15.6ms). When using SDRAMs the 82443BX can be configured via the Paging Policy
Register to keep multiple pages open within the memory array. Pages can be kept open in all rows
of memory. When 4 bank SDRAM devices (64Mb technology) are used for a particular row, up to
4 pages can be kept open within that row.
The DRAM interface of the 82443BX is configured by the DRAM Control Register, DRAM
Timing Register, SDRAM Control Register, bits in the NBXCFG and the eight DRAM Row
Boundary (DRB) Registers. The DRAM configuration registers noted above control the DRAM
interface to select EDO or SDRAM DRAMs, RAS timings, and CAS rates. The eight DRB
Registers define the size of each row in the memory array, enabling the 82443BX to assert the
proper CSA/B# pair for accesses to the array.
DRAM Organization and Configuration
The 82443BX supports 64/72-bit DRAM configurations. In the following discussion the term row
refers to a set of memory devices that are simultaneously selected by a CSA/B# or RASA/B# pair.
The 82443BX will support a maximum of 8 rows of memory when using SDRAMs in a desktop
configuration. Up to 6 rows of memory are supported when using EDO DRAM. A row may be
composed of discrete DRAM devices, single-sided or double-sided DIMMs.
The 82443BX has multiple copies of many of the signals interfacing to memory. The interface
consists of the following pins.
• Multiple copies
— MAA[13:0], MAB[12:11,9:0]# and MAB[13,10]
— CSA[7:0]#, CSB[7:0]#
— SRASA#, SRASB#
— SCASA#, SCASB#
— WEA#, WEB#
— DQMA[7:0], DQMB[5,1]
— CKE[5:0] (for 3 DIMM configuration)
4-14
82443BX Host Bridge Datasheet